Download 1. Summary and more Lecture notes Computer Architecture and Organization in PDF only on Docsity! Spring 2022 – Sinclair Computer Sciences Department University of Wisconsin-Madison CS/ECE 552 – Introduction to Computer Architecture Project Description 1. Summary The CS/ECE 552 term project is the complete functional design of a microprocessor called the WISC-SP22. All components of your design will be written in Verilog. As with the course homework assignments, the CS/ECE 552 Verilog restrictions apply, and all final code is expected to pass the Vcheck program. The project will be completed individually. The specifics of the microarchitecture and WISC-SP22 architecture are found in separate documents, and will also be posted on the course website. The project will progress in several distinct stages. Some of these stages are enforced through grading deadlines; others are not. The deadlines are: Date Project Component 2/21/22 Design Review (5% of project grade) 3/6/22 Phase #1 (15% of project grade) 4/3/22 Phase #2 (30% of project grade) N/A Phase #2.1 N/A Phase #2.2 4/8/22 Form Project Group 4/24/22 Phase #2.3 Caching (10% of project grade) 5/3/22 Phase #3 (30% of project grade) Each stage of the design makes the processor progressively more complicated. For your own benefit, it is strongly recommended that you not proceed to a new stage before you are confident the current stage is working to specification. Debugging errors in a complex design is much harder. It is almost always better to test smaller, simpler components first. Many of the Verilog problems in the homework assignments were designed to be compatible with the project. Please feel free to reuse these modules (of course, fixing any errors first!). In addition to the previous homework problems, you will be provided with several reusable modules that you can use in your design. Most of these are Verilog implementations of memory system components. Please note that these files do not follow the CS/ECE 552 Verilog restrictions, so don't include them when you run Vcheck. Download the project tar file (/u/s/i/sinclair/public/html/courses/cs552/spring2022/handouts/verilog_
