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2 Problems with Solutions on Advanced VLSI Design - Exam 1 | ECEN 6263, Exams of Electrical and Electronics Engineering

Material Type: Exam; Professor: Johnson; Class: ADV VLSI DES & APP; Subject: Electrical and Computer Engineering ; University: Oklahoma State University - Stillwater; Term: Fall 2002;

Typology: Exams

2010/2011

Uploaded on 07/17/2011

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Download 2 Problems with Solutions on Advanced VLSI Design - Exam 1 | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2002 Exam 1 WRITE YOUR NAME HERE Answ ov All questions must be answered on test paper! Open Book, Open Notes 1. Suppose a certain process has the following parameters. Ri = 3KQ, Ry, = 6KQ Rp, = 15SKQ, Ryn = SKQ a = 0.8um A 3 bus pair static RAM memory cell designed in this process is found to have the fol- lowing capacitive load on the bit line for each tmemory cell attached to the bit line. Chit/Neens = 20fF +. 3(fF/pm oe Find the transistor widths Wrcets Wncelts Wrpass for the 3 bus pair static RAM subject to the following constraints. ¢ For each transistor 32m <W<24um. © The read access “ should be as small as possible. Wyuth’ Sm Raut . (8) OQ Wap” Fiat V0 (u iu Ve) 5 3.30 oe" 2-3 ml co eee Ryall (use 2 Skye winpes By pass? ia ahs/ 3K 4 46 For mi peid bit ss delay i © © Whrpass = bee Wra -(2 “till = 2,2 Wal Fr Wn tise é null 2, thors! Walt s eH am te rpuns e\OE 2G oT AM (3) 22a il < Wath, Wapuas =(Rzrxzy 2 7 Wr > wan Wrell = o¢ Mm (7) ECEN 6263 Fali 2002 Exam 1 October 3, 2002 (300) 4) 2. Estimate the delays and power consumption in the circuit below using the RC model developed in class including the effects of the transistor threshold voltages V7, and Vp. Use as parameters the channel sheet resistances and the widths of the six transis- tors, W;, ..., Wg, and the node capacitances, C), ..., C4. You may assume that the capac- itances already contain all parasitics from the transistors and interconnect. a_[ile db x be pf To a. Answer the following when B = 1, D = 0 and A goes from 0 to 1. Rs Initial voltage acrossCj?__O Ra? Gy Final voltage across C;? 2 ¢ Initial voltage across C2?. Vad . x f, ‘1 a,¥ a (4 Final voltage across C2? 0 Bani, Initial voltage across C3?__O . t Gq 4 Final voltage across C3?, Vdd ‘ 2G z Initial voltage across C4? iV Bre - —~} ao Final voltage across C,?__ Vda, 4 KS £4 Delay from A to X? Oy 7 ON, Ed ax as gh + +42 WOM (4) i) * ws thas (Ei + fas.) Delay from A to Y? Liny= tdax * taxy M ANs tay? th)G4% 7 BGA ve (Fr RGR 1 Mebiel t Raf Pas 5 Ne, + (Ree + Ebr i Ue flay ‘October 3, 2002 1 Ah -lvool + Fe, Al“ we fd 2
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