2 Solved Problems on Advanced VLSI Design and Applications - Exam 1 | ECEN 6263, Exams of Electrical and Electronics Engineering

Download 2 Solved Problems on Advanced VLSI Design and Applications - Exam 1 | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2004 Exam 1 WRITE YOUR NAME HERE ArGW2v~ All questions must be answered on test paper! Open Book, Open Notes 1. Suppose a certain process has the following parameters. R, = 6KQ R, = 10KQ a= 03pm Vp = 08V Von = 5V A 3 bus pair static RAM memory cell designed in this process is found to have the fol- lowing capacitive load on the bit line for each memory cell attached to the bit line. Coit’ Nees = 4.08F + 1.0(8F um )¥, pass aFind the transistor widths Wp.on, Wreath Wnpase and the transistor lengths Li cetts Lacets Lypass for the 3 bus pair static RAM subject to the following constraints. Vuy > 0.167. tv Lnpass < 1.2um Now wrt Canine 5 Cred 2 Mp A on m (es -1) Gnpass wy tin /hpass Vig “Viv te = |b,7 7 nal Wh Ln tm oe «16.7 L pas (More space on next page) ECEN 6263 Fall 2004 Exam 1 October 8, 2004 1 ta male Wags srr} © ching vss: Jar “1h Zam / =(0y 0 (Ln abt DD 2 0.6m ” Speer f { we. te. - Gn pass p+e GnuMt ~ (+£njb ~ 6,56 4 Gajhe ; Ra wet /Ln wid “Re W ales /Lp pon se Mbpeetl = 636% Sa Woe nfs> = 6E¥ CG <4) “p ihn PISS 247 gm — Cwpath=YnigZ4>E (200m) b.For the transistor sizes you found in part a and the following constraints AV = Vy Nees = 32 what is the read access time? Natl 5 Wo AV UL =(6k ia oeWae 4 16-42)2 28. 2.36 . ™ | = LLY poee (es) -'0 = 224 xy ew ECEN 6263 Fall 2004 Exam 1 October 8, 2004 J May = 4). Bh = - 34 Cun pgs? oD lon,