Computer Architecture and Design Homework 6: MIPS Datapaths and Instruction Execution - Pr, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design Homework 6: MIPS Datapaths and Instruction Execution - Pr and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2008 Homework 6 Problems Assigned 10/6/07, due 10/13/07 Problem 1: Consider two types of MIPS datapaths. The clock rates for single-cycle and multicycle implementations are 250MHz and 1GHz, respectively. The following subroutine is used for estimating the performances. The argument register $a0 contains a very large positive integer (a million or greater: repeat beq $a0, $zero, finish beq $a0, $zero, finish beq $a0, $zero, finish addi $a0, $a0, –1 jump repeat finish add $v0, $a0, $zero Determine: (a) Average cycles per instruction (CPI) for two datapaths. (b) How much faster is the multicycle execution of the program (ratio of single-cycle to multicycle execution times)? Problem 2: Sketch a schematic showing a multicycle MIPS datapath for the execution of the jump and link (jal) instruction. In your schematic you may include only those units that participate in the execution of this instruction. Problem 3: The control for a multicycle MIPS datapath is implemented as a finite- state machine. Suppose, all possible 6-bit opcodes are classified into one of five types: 1. load or store 2. R-type 3. Branch type 4. Jump type 5. Illegal All illegal opcodes require the same action, i.e., exception, for which the control signals required by the datapath have been determined. Illustrate what modification you will make to the state diagram. Suppose the FSM is implemented with random logic and four flip-flops. Suggest a state assignment to reduce the dynamic power consumption, assuming that R-type is the most frequently executed instruction.