ECEN 6263 Fall '98 Exam 2: Circuit Analysis and Design - Prof. James Stine, Exams of Electrical and Electronics Engineering

Download ECEN 6263 Fall '98 Exam 2: Circuit Analysis and Design - Prof. James Stine and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall ‘98 Exam 2 WRITE YOUR NAME HERE __________________________________________ All questions must be answered on test paper! Open Book, Open Notes 1. Estimate the delays and power consumption in the circuit below using the first order RC model developed in class. Use as parameters the channel resistances of the six tran- sistors, , and the node capacitances, . You may assume that already contain all parasitics from the transistors and interconnect. a.When B=1, what is the delay from A to Y when A goes from 0 to 1? b.When B=1, what is the power consumption when A goes from 0 to 1? Assume that the probability that this happens is p every T seconds. R1 … R6, , C1 … C3, , C1 … C3, , M3 M2 M4 M5 M1 C3 C2 A B Y C1 M6 B ECEN 6263 Fall ‘98 Exam 2 November 9, 1998 1 c.Suppose that A=B and A and B both change at the same time so that a glitch may occur on the output Y. What is the power consumption when A=B goes from 0 to 1? d.Suppose that A=B and A and B both change at the same time so that a glitch may occur on the output Y. What is the power consumption when A=B goes from 1 to 0?ECEN 6263 Fall ‘98 Exam 2 November 9, 1998 2