4 Solved Problems in Final Exam on VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Download 4 Solved Problems in Final Exam on VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2001 Final WRITE YOUR NAME HERE ANSWER. All questions must be answered on (est paper! Open Book, Open Notes 1, In the circuit below, the node capacitances, C1, ..., C4, include all of the parasitic capacitance except the gate capacitances of the transistors. a. IfA=1,B=1, C= 0, write the conductance matrix, ial ; for the four voltages (V1, 4 V2, V3, V4) in terms of the channel conductances (not resistances) of the individual . transistors. Gt G2) Se ° » 0 [a] = -42 Ge ° 5 Oo © 0 (& a4Gq) -G4 ° © ~Gy ay ECEN 6263 Fall 2003 Final Deceenber 13, 2001 pose bof 7 4  b. IfA=1,B=1, C= 0, write the capacitance matrix, (al , for the four voltages (V1, Y V2, V3, V4) in terms of the node capacitances in the diagram (neglect gate capaci- tances). Oy ° ° oO Ce 0 ft oO 20 (oo ° oO Oo CH i | c. Redo the capacitance matrix in part b including the gate capacitances (Cys and C.7) of MS and M?. ey ob oO : o at x. fo (coscastas) ~4 59% 3594 0 -e4e oe atag ° 0 - hla, ° Cut $6aq YE HA=0,B=1,C=1, vite the conductance mati, [@] #or the four voltages (VI, ‘V2, V3, V4) in terms of the channel conductances (not resistances) of the individual transistors. Ge ~Gr oO ° Qs “G2 (@4G,) 0 ° ° oO oO 0 oO 0 oO GetGs, 4 e. IfA=0,B=1, C= 1, write the capacitance matrix, la , for the four voltages (V1, V2, V3, V4) in terms of the node capacitances in the diagram (neglect gate capaci- tances). Pic ° o o ©: ° Ca o ® 8 ° & 6 © © 3 cy HCEN 6263 Fall 2001 Final Docomber 13, 2001 page 2 of F le  3. Compare the performance of the pipelined and unpipelined multiplier shown below. mult stage 1 unpipelined multiplier mult stage 2 The delays of the components are delay (ns) 03 0.15 0.2 6.0 28 mult stage 2 | 3.1 a.Assuming the clock period.is as small as possible, what is the clock period for the unpipelined multiplier? Te may (Saye alin) + Tetah-ont t Tyla? Gor abr ase baer, b.What is the throughput for the unpipelined multiplier? L tee déyrd pues b Sri? /sew c.Assuming latency is the time for multiplier inputs to get clocked into the outputs of the top register until to the multiplier outputs are clocked into the bottom register, what is the latency of the unpipelined multiplier? TH 6.50 he d.Assuming the clock period is as small as possible, what is the clock period for the pipelined multiplier? Tene S41 dilty) t elrhnget Trt? B14 42 to 223 hater ¢. What is the throughput for the pipelined multiplier? too. . tt Piss pre a 27 xo! fee £Assumting latency is the time for multiplier inputs to get clocked into the outputs of the (op register until to the multiplier outputs are clocked into the bottom register, what is the latency of the pipelined multiplier? AT = Dt nee ECEN 6263 Fall 2001 Fina! Decembor 13, 2001 page 5 of7 a at component register set up register hold register clock to output unpipelined mult muit stage 1 4. Design a Booth recoded array multiplier for signed 24 bit inputs. You can use any 4s building blocks you like, but you must show the design of each block in terms of a logic function or a logic gate diagram. Hint: you do not have time to design an optimal Wal- lace tree, so use the same carry save tree for each bit position in the product. € 24 eed = VA SN sy Bwth toughen ¢ \ 4—~ 14 yeti PU CR Tae ey Porat Cap gra) Ey bepg Both Gedolenss gee Comp t 4.5) 3! HET eg beat, oy ext { t tere bier ede +E. he Sey SANT —— Paw poekid pool. she Telia be ECEN 6263 Fail 2001 Final December 13, 2001 page 6 of 7 hh — tons, WAL Sime CSA tre for pat od parton, Wome epee 3 (3,2), S13 corto 5 ok Haye aren C32 - TEOEN 6263 Pall 2001 Fiual Deoamber 13,2001 page 70f7 Lo