Download 4 Solved Problems on VLSI Design and Applications - Final Exam | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263
Fall 2002
Final
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All questions must be answered on test paper!
Open Book, Open Notes
1. Draw the simplified switching model, show the possible channel sheet resistance val-
ues and show the constraints on Vg and Vpg for the model to be valid in each case
below. Clearly indicate the location of the source, drain and gate of the FET.
a. nFET turned on: G
C switching model: oe /
4 Papa
Be RSS & ey 5
~ncintimenerseneise__— channel sheet resistance values:
1 constraints on Vgs and Vpg if any: in ‘ah 3 Ens
U ' », nFET tumed off: 7TH
switching model: \ G
sg»
channel sheet resistance values: Oc)
constraints on Vigg and Vpg if any: VGsS Mtn
( c. pFET tumed on: CG
4 switching model: |
gle ob Gi
s Lp
channel sheet resistance values: oh Rea, R
constraints on Vgs and Vpg if any: "As pA. "ps
t . ad pFET turned off: ae 4 Vip CIM, | >| Urpl)
sa LE 7)
channel sheet resistance values: <<
constraints on Vgg and Vpg if any: Ves ty z Ves] & Up ))
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‘ECBN 6263 Fail 2002 Final . December 11, 2002 page 1 of4
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+Ray (G4 Yt youre “5 )
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Ry (1-44) t (Ce rag ah ® 5, ert ltoy Sty t 24),
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b. falling edge on B to propagates to the output V4? ( A =| C2 )
switching model:
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,
dys titty i oppuscbe Pep.)
dynamic power dissipation: v 2 ~ i
4 pe Be Gag, +454 +t Sp) Vn“ Mp) ) 1 A My -G Me
3. Compare using the standard cell layout generator with hand layout.
a. List the advantages of using the standard cell layout generator.
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b. List the disadvantages of using the standard cell layout generator.
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ECEN 6263 Fait 2002 Final December 11, 2002 page 3 of 4
2 4, Design a 33,2 compressor for a Wallace tree out of 3,2 building blocks. You can use
Zs any building blocks you like, but you must show the design of each block in terms of
3,2 building blocks. Only design a single 33,2 compressor, not the entire carry save
tree.
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ECEN 6263 Fall 2002 Final December 11, 2002 page 4 of 4
