Download 4 Solved Problems on VLSI Design and Applications - Final Test | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263
Fali 2003
Final
WRITE YOUR NAME HERE Answ nv
All questions must be answered on test paper!
Opes Book, Open Notes
1. The layout below hss sometimes been used for a moderately large transistor to reduce
the drain capacitance.
THT [gg eee LD =
rr
drain active
a. What is the equivaient width of the transistor measured in the grid spacing, 4? For
simplicity, count the piece of poly (outlmed in dashed lines) that connects the gate to
/ Rte D4 naff = 27
"b, Uaing the premees (£24), (Soe), (Sa) (Cetas),(Sei=2) ana ite id sme
ing, 1, what is the drain capacitance to substrate?
Ca (Sg. gv-by +(Gl\4-0 + (8d 0
“(BL 30 ee) 14)
BCHN 6263 Pall 2003 Final December &, 2005 pape 1of6
7 tegen
ing, 3, what is the dmin to source capacitance (neglect gate capacitance}?
Ci Cord\ Dd
“9 . See
Fa amg te pms (5) (2 (ad) (St oe
ing, A, what is the drain to gate capacitance (neglect gate capacitance}?
Cay (Coyge) Dt
* Gg)
2 Suppose a transistor is coistracted with the same equivalent width as in problem 1, but
uses the standard layout below.
ol metal
: a re source mr
active
Boo drain
Do NOT use the width shown! Use the effective width from problem 1.
C, Cc
7 ue te pean (PG (SP Ci (wt
A A
ing, 4, what is the drain egpacitance to substrate? am
Che (esse De + DD) Ande 1209 1D +>)
+B) watt /
= fab) gor a(Ge\ 37> +h) 27%
b. B switches from Ito 0/A=1,C=1. t
S switching model:
delay |
V2 fhe Ret lyeg 1p +B Gy, (oA)
4 By Cog, (e¥27¥3)
PV thy Fg (Cyn, Jos + Relig lave Orn) HRA MG M4
Ngo" We ovicd SY2= WboTyy ov, o6 “Udy > Vad aYy sa My Men eof ee)
° Ey= Pes Re Ros fave Ry = Rnf/W
Ta tet tly “lo +245 +46 + Gu)
+ Rs az (% + yy + we Ura ~e Be Bl Vis)
> Pheu | ' ,
go Ee | “ay (Yu Ca G34 190g + Gy, (2
K+ Sag Way + a Gm) l va Ve) |
BCEN 6263 Fall 2003 Final Decomber §, 2043 page 5 of
4, Design a 32-bit adder with a worst case delay proportional to log. You can use any
building blocks you like, but-you must show the design of each biock in terms of tran-
sistor symbols.
a, bo
de aby
Carry cha or hanks
ee
page dois
Af, Gaps
‘ta Pio Ge fe “3 '
die he og Pa “6
34 Py } Gs Pos
31% Lr titra eles
a4 TP Tt a G fea
45 I< Pf. LTT TTT | © Re
sm oA ET Ce
P
