42 Unsolved Questions on Computer Architecture | CSCI 4717, Exams of Computer Architecture and Organization

Download 42 Unsolved Questions on Computer Architecture | CSCI 4717 and more Exams Computer Architecture and Organization in PDF only on Docsity! Points missed: _____ Student's Name: __________________________________ Total score: _____ /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 4717 – Computer Architecture TEST 1 for Fall Semester, 2007 Section 001 Read this before starting! The total possible score for this test is 100 points. This test is closed book and closed notes Please turn off all cell phones & pagers during the test. You may use one sheet of scrap paper that you will turn in with your test. When possible, indicate final answers by drawing a box around them. This is to aid the grader. Failure to do so might result in no credit for answer. Example: If you perform work on the back of a page in this test, indicate that you have done so in case the need arises for partial credit to be determined. Binary Hex Binary Hex Power of 2 Equals 0000 0 1000 8 2 4 16 0001 1 1001 9 2 5 32 0010 2 1010 A 2 6 64 0011 3 1011 B 2 7 128 0100 4 1100 C 2 8 256 0101 5 1101 D 2 9 512 0110 6 1110 E 2 10 1K 0111 7 1111 F 2 20 1M 2 30 1G “Fine print” Academic Misconduct: Section 5.7 "Academic Misconduct" of the East Tennessee State University Faculty Handbook, June 1, 2001: "Academic misconduct will be subject to disciplinary action. Any act of dishonesty in academic work constitutes academic misconduct. This includes plagiarism, the changing of falsifying of any academic documents or materials, cheating, and the giving or receiving of unauthorized aid in tests, examinations, or other assigned school work. Penalties for academic misconduct will vary with the seriousness of the offense and may include, but are not limited to: a grade of 'F' on the work in question, a grade of 'F' of the course, reprimand, probation, suspension, and expulsion. For a second academic offense the penalty is permanent expulsion." 1. If security is a critical performance measure for a component of a system design, which would you rather implement the component in, hardware, firmware, or software? In a sentence or two, justify your answer. (2 points) 2. Which method of component implementation is the cheapest to manufacture, hardware, firmware, or software? (2 points) a.) Hardware b.) Firmware c.) Software 3. For the following items, indicate whether the characteristic more closely describes a top-down (TD) or a bottom-up (BU) design method. (1 point each) ____ You're under a time crunch to get a project done quickly ____ The design needs to precisely follow existing industrial standards ____ There are critical performance goals that need to be met For the following 3 problems, identify which of the following system functional diagrams, a, b, c, or d, best describes the operation of the example system or application. Note: Focus only on the immediate system described. Do not include external components such as devices across a network that may work with the system. (2 points each) 4. A kiosk that simply displays information sent to it from across a network: ________ 5. An encoder converting raw stored video to MPEG then storing it back to the hard drive: ________ 6. An encoder converting raw live video to MPEG then storing it to the hard drive: ________ 7. Name three of the five effects discussed in class that Moore’s law has had on the contemporary application of computers. (4 points) I/O Control Storage Process -ing I/O Control Storage Process -ing I/O Control Storage Process -ing I/O Control Storage Process -ing a.) b.) c.) d.) 19. Which cache mapping function does not require a replacement algorithm? (2 points) a.) Direct mapping b.) Set associative mapping c.) Fully associative mapping 20. Assume a memory access to main memory on a cache "miss" takes 20 ns and a memory access to the cache on a cache "hit" takes 4 ns. If 75% of the processor's memory requests result in a cache "hit", what is the average memory access time? Show your work if you are worried about your math. (2 points) a.) 3 nS b.) 4 nS c.) 6 nS d.) 10 nS e.) 20 nS f.) 24 nS 21. Which cache write mechanism creates more bus traffic? (2 points) a.) Write through b.) Write back 22. Which cache write mechanism allows an updated memory location in the cache to remain out of date in memory until the block containing the updated memory location is replaced in the cache? (2 points) a.) Write through b.) Write back c.) Both d.) Neither 23. What is the simplest solution to prevent problems with a multiprocessor/cache system from having invalid data in one of the caches? Hint: it isn’t write through or write back and it’s not very efficient. (2 points) 24. True or false: Like the memory hierarchy, the mezzanine bus structure places the faster busses closer to the processor. (2 points) 25. Give an example of a device that would be attached to the processor’s local bus. In the Pentium organization, this would be between the Northbridge and the processor. (2 points) 26. List two of the three problems discussed in class that occur when the number of devices on a single bus increases. (3 points) 27. Give an example of a device that would be well-suited to an x32 PCI-E slot. (2 points) 28. Of the following characteristics, identify by placing a checkmark in the appropriate column whether the characteristic describes PCI, PCI-X, and/or PCI-E. Some rows (characteristics) will have more than one checkmark. (Each row is worth 1 point) Characteristic PCI PCI-X PCI-E Transmits data and control serially    Uses differential signalling similar to Manchester encoding to allow for long distance communication    Supports the PCI command structure making it compatible with legacy software. (Check one or both)   29. What is the purpose of bus arbitration? (3 points) 30. The graphic to the right depicts the digits of a 4-bit Hamming code where a single bit error has occurred. Circle the bit that has flipped. (2 points) 31. True or false: The graphic to the right depicts the digits of a 4-bit Hamming code with parity where a double bit error has occurred. (2 points) 32. How many check code (parity) bits would you need to provide single error correction for 48 data bits? (2 points) a.) 2 b.) 3 c.) 4 d.) 5 e.) 6 f.) 7 g.) 8 h.) 9 i.) 10 33. Which DRAM technology overlaps data read with column address write for next read, i.e., they happen simultaneously? (2 points) a.) Fast Page Mode b.) Extended Data Out c.) Both 34. Which DRAM technology uses fixed row address for multiple column reads? (2 points) a.) Fast Page Mode b.) Extended Data Out c.) Both 0 1 1 0 1 0 0 1 0 0 1 1 0 1 0 35. The table below describes the position number of the data and code bits of a single error correction code for eight data bits D7, D6, D5, D4, D3, D2, D1, and D0. Determine the equations to derive P3, P2, P1, and P0 from D0 through D7. (4 points) Bit position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Position number 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 Data bit not used not used D7 D6 D5 D4 D3 D2 D1 D0 not used Check code bit P3 P2 P1 P0 P3 = P2 = P1 = P0 = 36. For the error correcting system of the previous question, assume that the check code retrieved from memory was 0101 and the newly calculated check code on the data retrieved from memory was 1110. Assuming a single bit error has occurred, which bit was the one that flipped, D7, D6, D5, D4, D3, D2, D1, D0, P3, P2, P1, or P0? (2 points) 37. The translation lookaside buffer (TLB) is basically a cache for page tables. A TLB "miss" is a request for a page that isn't in the TLB. Name one way that we can reduce the chances of a TLB miss. (3 points) 38. Using paging with 10 processes and a page size of 4K (4096) words, what is the most memory that is wasted? (2 points) 39. What problem is caused by small pages in virtual memory? (2 points) 40. True or false: In virtual memory, the size of a page in a program’s logical space is the same as the size of a frame in the physical memory space. (2 points)