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CS433: Computer Architecture Homework 1 - Spring 2009, Assignments of Computer Architecture and Organization

The instructions and problems for homework 1 of the computer architecture course offered by the university of california, berkeley in spring 2009. The homework includes multiple-choice questions, calculations, and identification of data hazards in a given code sequence. It also includes a graduate problem regarding the implementation of register-memory alu operations in the risc pipeline.

Typology: Assignments

Pre 2010

Uploaded on 03/11/2009

koofers-user-9ig
koofers-user-9ig 🇺🇸

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Download CS433: Computer Architecture Homework 1 - Spring 2009 and more Assignments Computer Architecture and Organization in PDF only on Docsity! CS433: Computer Architecture – Spring 2009 Homework 1 Total Points: 18 Points (undergrad), 28 Points (graduate) Due Date: Feb. 5, 2009 by 2:00 pm (See course information handout for more details on late submissions) Directions: · Please read the course information handout for information on groups and collaboration and other homework policies. · On top of the first page of your homework solutions, please write your name(s) and NETID(s), and whether you are a 3-hour or 4-hour student. On each successive page, write your NETID(s). · Please show all work that you used to arrive at your answer. Answers without justification will not receive credit. · On Campus Students: please submit the homework in class. · I2CS Students: please submit the homework to levine@uiuc.edu. Use the subject line: “CS 433 HW 1 Handin”. Make sure your NETID(s) are on each page. Problem 0 (3 points) Answer these three multiple-choice questions: 0.1) You are offered old homework solutions by a student who formerly took this class. You should: a. Accept the solutions because no one will ever know. b. Not even look at the solutions because that is the honor code set for this class. c. Accept the solutions because you don’t really want to learn anything in this class. You are simply taking it to fulfill a requirement. 0.2) While working with a partner on a homework assignment, one of your classmates asks if he/she can also work with you. You should: a. Tell the other student that you already have a partner for this homework assignment. b. Agree to work with the other student, but only on the portion of the homework you have not yet completed. c. Apologize for having found a partner too early and offer to send the other student a completed copy of your homework. 0.3) Suppose you and your partner are overwhelmed with work at the time the homework is due. You should: a. Have your partner do half the problems, you do the other half, and combine your solutions. b. Complain about your course load to everyone you meet. c. Think ahead and email Professor Adve for an extension within 48 hours of when the homework is handed out. Problem 1 (4 points) Consider a 0.25 cm2 die for a 32-bit processor manufactured from a 30cm-diameter wafer costing $6,000. Assuming a wafer yield of 98%, 0.4 defects per cm2, and α=4, what is the expected cost per die (before testing)? Problem 2 (2 points) Two enhancements are proposed: one that can enhance 60% of execution time with a speedup of 1.5, and another that can enhance a different 25% of execution time with some greater speedup value. Only one of these two can be implemented. How much of a speedup is necessary in the second enhancement to give a better enhancement than the first? Problem 3 (2 points) Several researchers have suggested that adding a register-memory addressing mode to a load-store machine might be useful. The idea is to replace sequences of LOAD R1, 4(R8) ADD R2, R2, R1 with ADD R2, 4(R8) Adding the new instruction will cause the clock cycle time to increase by 15% and does not affect CPI. If 26% of all instructions are loads, what percentage of these loads must be eliminated for the machine with the new instruction to have at least the same performance? Problem 4 (7 points) Identify the data hazards in the code below. Assume the 5-stage pipeline from A.1. For each hazard, state whether it requires a stall to be handled, or can be handled via forwarding. 1: LD.D R1, 0(R6) 2: LD.D R2, 4(R6) 3: DADD R1, R1, R2 4: DMUL R3, R2, R1 5: DSUB R2, R2, R3 6: DSUB R1, R4, R3 7: ST.D R1, 0(R6) 8: ST.D R2, 4(R6)
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