Download 9 CMOS Dynamic Logic Circuits - Lecture Slides | ECEN 4303 and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity! C. Hutchens Chap 9 ECEN 4303 Handouts 1 Chapter 9 CMOS Dynamic Logic Ckts Dynamic Pass Gate Circuits Domino Logic Zipper CMOS Single Phase C. Hutchens Chap 9 ECEN 4303 Handouts 2 Dynamic t-gate logic • Data must be a valid Logic level by the falling edge of the clock • Clock period must be greater than the sum of a) the worst case clock skew plus b) the worst case propagation delay of the pass or t-gate logic and c) the Active logic (Inverter in the example0. • Clock period must be shorter than the decay time if the holding node. C. Hutchens Chap 9 ECEN 4303 Handouts 5 Domino Logic • Data must be a valid Logic level by the falling edge of the. • Clock period must be greater than the sum of 1) the worst case clock skew for the H clk layout 2) the worst case propagation delay of the NMOS logic and the Active logic (Inverter, NAND, NOR, etc.) in the example, and 3) precharge time. • Powerfully Minterm or Maxterm rich a single NOR, NAND, XOR or AND-OR-INV gate can combined over 128 terms in two gate delays of less than 1000pS today or potentially at a 10GHz rate in the future. Note all of these gates result in the NMOS array being off during precharge. C. Hutchens Chap 9 ECEN 4303 Handouts 6 Charge Sharing in Domino CMOS Charge sharing might look like improper timing but it is a different phenomena and is a result of charge on the dynamic logic node being shared with the D-B capacitance terms the NMOS array. q C V C LC W W VLogic L DD dbp ox n p DD= = + +( ( )) V q C C C LC W W V C Co Logic L s dbp ox n p DD L s = + = + + +( ) ( ( )) ( )2 2 Cs can consist of as many as 13 Cdb terms C. Hutchens Chap 9 ECEN 4303 Handouts 7 Charge Sharing in Domino CMOS Example Assume 1) Inverter is minimum geo., 2) Cdbn ≈ Cgsn/2 ≈ 2um (2fFd/um) /2 = 2fFd, 3) Cdbp = 2 Cgsp = 8fFd, 4) the NMOS evaluation transistor is 2 Wmin and 5) the PMOS precharge transistor is 2 Wmin Determine Vo for a worst case of a 3X4 NMOS array of minimum geometry transistors. Cs = 3x3 Cdb + Cdbeval = 18fFd + 2x2fFd = 22fFd CL = Cdbp + 3Cdbn + CINV = 8fFd + 6fFd + 2x2x2fFd CL = 22fFd ( ) VfFdfFd fFd CC VCV sL DDL o 65.12222 3.322 )( = + • = + = Design will fail Fix Increase CL “Beta” match INV, and Inc. precharge Width by 6. Now CL = 48fFd + 6fFd + 14fFd = 68fFd. ( ) V C V C C fFd fFd fFd Vo L DD L s = + = • + = ( ) . . 2 68 33 68 22 25 Vo s.b. > 70% VDD = 2.45V C. Hutchens Chap 9 ECEN 4303 Handouts 10 Single Phase Logic C. Hutchens Chap 9 ECEN 4303 Handouts 11 Final PROJECT C. Hutchens Chap 9 ECEN 4303 Handouts 12 Final PROJECT
