Review Problems for Chapter 2 in ECE 4430: Analog Integrated Circuits and Systems, Study notes of Electrical and Electronics Engineering

Download Review Problems for Chapter 2 in ECE 4430: Analog Integrated Circuits and Systems and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-1 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 LECTURE 215 – CHAPTER 2 – REVIEW PROBLEMS (READING: Text-Chapter 2) Chapter 2 Topics • Integrated Circuit Technology • Bipolar Technology • Passive Components in Bipolar Technology • CMOS Technology • CMOS Technology-Compatible Devices • BiCMOS Technology Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-2 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 1 (a.) Sketch the approximate side view of a NMOS transistor in a p-substrate. Identify each region and identify the connections at the top surface of the integrated circuit for the source, drain, gate and bulk/substrate. Solution n+ n+ Polysilicon p+ p- substrate Lightly Doped p Heavily Doped n Heavily Doped p Lightly Doped n Intrinsic Doping Fig.3.1-01 Bulk/Substrate Source Gate Drain Thin Oxide (10-100nm 100Å-1000Å) Metal Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-3 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 1 - Continued (b.) Sketch the approximate side view of a NPN vertical transistor in an n-epitaxial region which is on top of a p-substrate. Identify each region (including the n+ buried layer) and identify the connection at the top surface of the integrated circuit for the base, emitter, collector and substrate. Solution p substrate p+ isolation p base n+ emitter n+ buried layer n collector n+ p+ p + isolation p+ p p- ni n- n n+ Metal SIDE VIEW Substrate Collector Base Emitter Su00E2S4B Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-4 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 2 A layout of a NMOS transistor is shown. (a.) Find the values of RD, and RS in the schematic shown if the sheet resistance of the n+ is 35 Ω/sq. and the resistance of a single contact is 1Ω. (b.) Find the values of CBD and CBS assuming the transistor is cutoff and the drain and source are at ground potential if CJ and CJSW for an NMOS transistor are 770x10-6 F/m2 and 380x10-12F/m. Assume the capacitors are lumped and appear on the source/drain side of the bulk resistors in part (a.). (c.) What is the W and L of this transistor? (d.) If the overlap capacitor/unit length is 220x10-12F/m, what is CGD? n+ Metal Poly Contact p-substrate Each square is 1µm x 1µm Fig. F00E2P1 Blue RedBlack White White External Drain External Source External Gate RD RS External Drain External Source External Gate CBD CBS Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-9 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 4 - Continued Next, we must find the area and perimeter of each drain. AD1 = 60µm2 & PD1 = 32µm AD2 = 120µm2 & PD2 = 52µm Cbd1 = CJ·AD1         1+ 2.5V 2|φF| MJ + CJSW·PD1         1+ 2.5V 2|φF| MJSW = 770x10-6·60x10-12       1+ 2.5V 0.8 0.5 + 380x10-12·32x10-6       1+ 2.5V 0.8 0.38 Cbd1 = 22.75fF + 7.10fF = 29.84fF Cbd2 = CJ·AD2         1+ 2.5V 2|φF| MJ + CJSW·PD2         1+ 2.5V 2|φF| MJSW = 560x10-6·120x10-12       1+ 2.5V 0.7 0.5 + 350x10-12·52x10-6       1+ 2.5V 0.7 0.35 Cbd2 = 31.43fF + 10.69fF = 42.12fF Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-10 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 5 A CMOS circuit is shown. Assume a p-well CMOS technology and draw the complete layout for the NMOS and PMOS transistors that has minimum rectangular area for the source and drain diffusions. Some pertinent design rules are listed below. DR1 = distance from the square contact to diffusion from polysilicon = 2µm DR2 = all contacts are to be square with a dimension of 2µm by 2µm DR3 = the overlap of the contact by the diffusion or poly = 2µm DR4 = min. separation between n+ diffusion and p-well = 2µm DR5 = minimum overlap of contact by metal = 1µm DR6 = poly must overlap the channel by 1µm All metal widths are to be 4µm. Put as many contacts between the metal and diffusions as possible. Show the metal connections between transistors and indicate where metal goes for connections from transistors to external connections (vin and vout must be in metal). Use the indicated scheme below for identifying the various regions. If you wish to use colored pencil, use the scheme below or indicate which colors pertain to which region. +5V voutvin 20µm 2µm 10µm 2µm M2 M1 F99E1P1A Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-11 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 5 – Continued Solution n+ p+ Metal Poly p-well n-substrate Each square is 1µm x 1µm Fig. F99E1S1B Blue RedBlack OrangeGreen White 5V vin vout Ground M2 M1 Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-12 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 6 This problem consists of a number of short questions 1. What is the resistance of the drain if the sheet resistance of n+ diffusion is 10Ω/sq.? What is the drain-bulk capacitance assuming VBD =0V if bottom capacitance is 0.33pF/µm2 and the sidewall capacitance is 0.9fF/µm? Rn+ ≈ 10Ω/sq.x 8 7 =11.43Ω Rn+ = 11.43Ω CBD = 0.33pF/µm2x70µm2 + 0.9fF/µmx34µm = 23.1fF+30.6fF = 53.7fF CBD = 53.7fF 2. Why are contacts normally square and minimum size? They are square because that is minimum area and they are minimum size because different size contacts do not etch evenly so small contacts are chosen for minimum contact area. Larger contacts are done by repeated use of minimum size contacts._ 3. What is the function of the field oxide (FOX) in a CMOS technology?__The function of field oxide is to isolate the substrate from conductors on the surface. 1µm Drain Diffusion Po ly si lic onMetal Contacts F99E1P3A Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-13 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 6 – Continued 4. How are two BJT transistors fabricated in the same substrate electrically isolated from each other? Each BJT is fabricated in its own n-epitaxial region surrounded on all sides by p material. This pn junction is reversed biased to electrically isolate the two transistors.________________________________________________________ 5. Assume that a 1kΩ resistance of an IC process has a voltage coefficient of -1000ppm/V. What is the resistance value if the average voltage across the resistor is increased from 0 to 5V? R(5V) =R(0V)- 1000 1,000,000 5Vx1000Ω = 1000Ω-5Ω = 995Ω R(5V) = 995Ω 6. List the 5 capacitances associated with the MOSFET operating in the saturation region and tell whether this capacitance is depletion or parallel plate or both. 1.) Gate -drain which is parallel plate___________________________________ 2.) Gate-source which is both parallel plate and depletion___________________ 3.) Bulk-drain which is depletion______________________________________ 4.) Bulk-source which is depletion_____________________________________ 5.) Gate-bulk which is parallel plate____________________________________ Lecture 215 – Chapter 2 – Review Problems (12/16/01) Page 215-14 ECE 4430 - Analog Integrated Circuits and Systems © P.E. Allen - 2001 Problem 7 A top view of a CMOS push-pull amplifier is shown. Find the numerical value of all capacitances shown on the schematic. Assume that the dc value of the output is 2.5V and the MJ and MJSW is 0.5 for both transistors. n+ p+ Metal Poly p-well n-substrate Each square is 1µm x 1µm F99FEP2B Blue RedBlack OrangeGreen White 5V vin vout Ground M2 M1 CBD1 CBD2 CGS1 CGS2 CGD2 CGD1 vin vout M2 M1 VDD = 5V F99FEP2