A Circuit with Feedback - Lecture Slides | CPSC 5155G, Study notes of Computer Architecture and Organization

Download A Circuit with Feedback - Lecture Slides | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! Chapter 6 Flip-flops & Sequential Circuits A Circuit With Feedback Feedback depends on the idea of gate delay, that the output of a gate does not change instantaneously with the input. Sample circuit. ¥ v +% x— ot Z oy we? Let “Y” denote the output of the AND gate. If X = 0, Y = 0,and Z= 1. This isa static situation. Consider what happens if X = 1. After one gate delay, we have Y = 1 and after two Z = 0. Page | of 14 CPSC 5155 Jamaary 28, 2006 ee? of egy A Circuit With Feed back(continued) Chapter 6 Flip-flops & Sequential Circuits 0. 1 2 3 4 5 | Gate Delays om ¥ Z i+ y Z Xx 5 x NY Zz INy Rg Inv. ¢ Inv. Z x 3 X Xx 5 Page 2 of 14 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits Flip-Flops & Clocked Flip-Flops A flip-flop is a binary circuit that stores a single bit: 0 or 1. A synchronous flip-flop is one that reacts to its input only at a specific phase of the clock. By Q(T), we denote the state of the flip—flop at the present time. Either Q(T) = 0 or Q(T) = 1. By Q(T + 1), we denote the state of the flip—flop at the next time. In general, Q(T + 1) depends on Q(T) and the input to the flip—flop. The exact dependency determines the type of flip—flop. Page 5 of 14 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits Structure of a Flip-Flop: Plain and Clocked a a > Q Q R R This is an S—R (Set Reset) flip flop The “plain version” reacts to input any time the input changes This version of a clocked SR reacts only when the clock is high. This makes circuit design more predictable; no “race” conditions. Functioning of all flip-flops depends on the gate delay. We do not concern ourselves with the internal structure. Page 6 of 14 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits Characterizing Flip-Flops There are one or two inputs and two outputs. The two outputs are the state Q(T) and its complement: Q(T) amt awry Two tables Characteristic How the next state is determined by the present state and input. Useful for circuit analysis. Excitation Given the present state and desired next state, what should the input be? Useful for circuit design. Page 7 of 14 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits The JK Flip-Flop An improved SR flip-flop. Two inputs: J and K. a7 QT) 4K ODE Characteristic table J K Q(T +1) 0 0 Q(T) — no change 0 1 0 1 0 1 1 1 Q(T) — the complement J=1 and k = 1 forces the JK flip-flop to change its state. Page I0 of 16 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits The JK Flip-Flop (Excitation Table) We make use of the flexibility offered by allowing J = 1 and k = 1. a7) OMe 4K Qa) Excitation Table Q(T) | Q(T+1) J kK 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d Q(T) = 0 J=1K=0=5 next state is 1. J=1K=1= next state is 0’ or 1. Page I of 16 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits The D Flip-Flop Q(T)- 4D aD Characteristic Table ———1.——— D QT + = Excitation Equation D=Q(T+1) Whatever you want the next state to be determines the input. The name “D” stands for “Data”. The flip-flop can be used as a simple data store. Itis useful for memory & interface to I/O. Page 12 of 16 CPSC 5155 Jamaary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits The JK as a General Flip-Flop The JK flip-flop can easily be wired to act either as a T flip-flop orasaD flip-flop. It is the most general flip-flop. K ODE T JK Qt) 0 00 Q(T) 1 11 Q(T) MEED ASYrCHROVeDS Page 15 of 16 CPSC 5155 D J Qtr K QT) D JK ott) 0 0 1 0 | 1 0 | CLEAle, Jamary 28, 2006 Chapter 6 Flip-flops & Sequential Circuits The Master—Slave Flip-Flop Name is politically incorrect, but cannot be improved upon. Example: A master-slave JK flip—flop using an SR as the “slave” Fu Clock ho “LS If the JK “master” flip—flop is functioning correctly, the “slave” SR never gets S=0, R=OorS=1,R=1. Clock is high “master” flip-flop reacts to input “slave” flip-flop does not react to input Clockis low “master” flip-flop does not react to input “slave” flip-flop reacts to change in the “master”. Page If of 16 CPSC 5155 Jamaary 28, 2006  Cord —_- Clouds ly hen Lory CLE co cueso lip Tbr 2} Jove? SL fses bat Aevse Title: Jan 30 - 7:07 PM (17 of 17)