Adders - Advanced VLSI Design - Lecture Notes | ECEN 6263, Study notes of Electrical and Electronics Engineering

Download Adders - Advanced VLSI Design - Lecture Notes | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Adders fig. 10.1a, p. 638 half-adder Table 10.1, p. 638 truth table eq. 10.1, p. 639 logic equations fig. 10.2, p. 639 implementation fig. 10.1b, p. 638 full-adder Table 10.2, p639 truth table eq. 10.2, p. 639 logic equations fig. 10.3, p. 640 implementation fig. 10.12, p.645 (a) multi-bit adder out of full adders, (b) no inverter in carry chain by alternating cells with inverted inputs. These type of multi-bit adders are called Ripple Carry Adders since the carry signals must propagate through the full adder cell in each bit. Clearly, the carry chain is the path with the longest delay. Carry chain delay can be mini- mized by minimizing the Cin to Cout delay of each full adder cell (the carry chain is the longest delay in multi-bit adders). Even though all of A,B,C inputs are functionally equiv- alent, we arbitrarily choose C for the carry in. We will minimize the delay on the C input and not care if the delays on the A,B inputs are increased because they do not impact carry chain delay. eq. 10.3, p. 639 Refactored logic equation for S eliminates need for inverted inputs. fig. 10.4, p. 641 allows reduced transistor count implementation. fig. 10.5a, p. 642 typical standard cell layout fig. 10.5b, p. 642 (and inside front cover) typical data path layout These layouts are too slow for multi-bit adders when Nbits > 4. Carry Chain Optimization. Recall that optimum gate size for maximum speed is two or three inputs. Can improve speed by using less complex gates in the carry chain. Note that the full adder in fig. 10.4, p. 641 contains many parallel and series combinations of FETs with A, B inputs. Carry chain delay can be reduced by replacing these FET combinations with single FETs. A B => A B => A B⋅ A B+Adders October 29, 2006 page 1 of 9 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n More generally, the G, P, K functions defined in Table 10.2, p. 639 can be used. From the truth table Carry Generate: G A B⋅= Carry Propagate: P A B⋅ A B⋅+ A B⊕= = Carry Kill: K A B⋅= so that eq. 10.2, p. 639, can be rewritten S P Cin⊕= Cout G P Cin⋅+= Cout K P Cin⋅+= fig. 10.15, p.648 every bit except LSB must wait longer for carry than A, B inputs. Can compute P, G and K while waiting for Cin. A design with gate inversions taken into consideration. A B G P Cin Cout Half Adder S optimized ripple carry fig. 10.16, p. 649 delay of the ripple carry adder proportional to Nbits (each gray box cor- responds to AND-OR gate on the carry chain) fig. 10.18, p. 652 pass transistor carry chain. Carry kill, carry generate and carry propagate are mutually exclusive (only one can be “1” at any time) which allows the circuit to work Adders October 29, 2006 page 2 of 9 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n 2. Provide double rail C, C carry chain. G P Cin Cin Cout Cout HA to sum gate to sum gate Complementary XOR implementation. a b ab ab+=⊕ a b+( ) a b+( )= pull down can use: a b b a a b b a or extra contact! bigger, slower implies Use the form without extra connection for pull down and pull up circuit to achieve opti- mum area and speed:Adders October 29, 2006 page 5 of 9 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n b a b a a b⊕ b b a a no contact here a b a bVdd Gnd a b⊕ Look Ahead Carry. fig. 10.12, p. 645 notation for the multi-bit adder which labels the LSB as bit 1 instead of the customary bit 0. They also define Ci as the carry out of bit i, C0 = Cin, CN = Cout. eq. 10.9, p. 648 Ci can be determined from Ci-1where Gi AiBi= Pi Ai Bi⊕= Substituting for Ci-1 gives Ci Gi Pi Gi 1– Pi 1– Ci 2–+( )+= Gi PiGi 1– PiPi 1– Ci 2–+ += Gi:i 1– Pi:i 1– Ci 2–+=Adders October 29, 2006 page 6 of 9 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n where Gi:i 1– Gi PiGi 1–+= Pi:i 1– PiPi 1–= are the group size 2 generate and propagate functions. We can continue to substitute for Ci-2 to get the group size 3 generate and propagate func- tions. Ci Gi:i 1– Pi:i 1– Gi 2– Pi 2– Ci 3–+( )+= Gi:i 1– Pi:i 1– Gi 2– Pi:i 1– Pi 2– Ci 3–+ += Gi:i 2– Pi:i 2– Ci 3–+= where Gi:i 2– Gi:i 1– Pi:i 1– Gi 2–+ Gi PiGi 1– PiPi 1– Gi 2–+ += = Pi:i 2– Pi:i 1– Pi 2– PiPi 1– Pi 2–= = By induction, the group size n generate and propagate functions are Gi:i n– 1+ Gi:i n– 2+ Pi:i n– 2+ Gi n– 1++= Gi Pi Gi 1– Pi 1– … Gi n 2+– Pi n– 2+ Gi n– 1++( )…( )+( )+= Pi:i n– 1+ Pi:i n– 2+ Pi n– 1+= PiPi 1– …Pi n 2+– Pi n 1+–= Thus, the carry look ahead scheme gives a very simple circuit to calculate every carry, Ci, Ci Gi:1 Pi:1C0+= C0 Cin≡( ) but hides the difficulties in the calculation of the group generate and propagate. fig. 10.19, 10.20, p. 652 If we use our rule of thumb of no more than 4 series transistors in a logic gate, then we can have fast gates for up to group size 3 generate and propagate functions (one of the series transistors comes from the inverter on the input). Adders with more than 3 bits can use carry chain made up of a cascade of group size 3 generate and propagate gates (Manchester Carry Chain). Gi,Pi XOR C0C3C6C9C12C15 P1 XOR Gi,Pi XOR Gi,Pi XOR Gi,Pi XOR Gi,Pi XORAdders October 29, 2006 page 7 of 9