Download Address Instruction-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! 1-address instruction Code size = 1+3= 4 bytes # of bytes accessed from memory 4 bytes for instruction fetch + 3 bytes for source operand fetch + 0 bytes for storing destination operand Total = 7 bytes 1 byte 3 bytes op code source 2 docsity.com 0-address instruction Code size = 1 bytes # of bytes accessed from memory 1 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 10 bytes 1 byte op code docsity.com RISC and MIPS ISA …Cont’d Supports … cont’d Instructions: - Data Transfer: load, store, register-register move - Simple Arithmetic: add, subtract, and shift - Compare: equal, not-equal, less - Branch: PC-relative, jump and call/return Designed for pipelining efficiency docsity.com MIPS Instruction Word format Recap: MIPS types and size of operands Types of an Operand - Integer - Single-precision floating point - Character Size of Operand - Character 8-bit - Half word 16-bit - Single precision FP or Word 32-bit - Double precision FP or 64-bit double word docsity.com MIPS Instruction Word Format Op 31 26 0 15 16 20 21 25 Rs Rt Rd Func Register-Register (R-Type) 5 6 10 11 Sht Op-code = 000000 Rs and Rt : source operand registers Rd : Result carrying register Sht: Number of bit-shift –(left/right) Func: ALU function to encode the data path operation Execution: Rd <- Rs func Rt docsity.com MIPS Operations Immediate Arithmetic / Logical Instructions Instruction Name Meaning DADDIU R1, R2, # 30 Add unsigned Imm Reg[R1]<-Reg[ R2]+Reg[R3] Load/Store Instructions Instruction Name Meaning LW R1, 30 (R2) Load word Reg[R1]<-Mem [30+Reg[ R2] SW R1, 30(R2) Store word Mem [30+Reg[R2]<- Reg[R1] DADDIU 31 26 0 15 16 20 21 25 R2 R1 30 LW/SW 31 26 0 15 16 20 21 25 R2 R1 30 docsity.com MIPS Instruction Word Format Op 31 26 0 15 16 20 21 25 Rs Rt immediate Branch /Jump Register Conditional Branch Instructions: (i) used after the compare or test BEQZ: Rs is the register and Rt is unused; Condition test the register for Zero or non-zero (ii) Condition with the Branch; BNE Rs and Rt are compared iii) Jump Register; Jump and Link Register Rt=0, Rs = Destination and immediate = 0 docsity.com MIPS Operations Branch/Jump Register Instruction Name Meaning BEQZ R4, name Branch equal zero If Reg[R4]=0 then PC <- name BNE R4, R3, name Branch not equal zero If Reg[R4]!=Reg[R3] then PC <- name JR R4 jump register PC<- Reg[R4] JALR R4 Jump and Link Register Reg [R31] <- PC+4; PC<- Reg[R4] BEQZ 31 26 0 15 16 20 21 25 R4 xxxx (PC+4)-217 <= name< (PC+4)-217 BNE 31 26 0 15 16 20 21 25 R4 R3 (PC+4)-217 <= name< (PC+4)-217 JR/JALR 31 26 0 15 16 20 21 25 R4 0000 0000 …. 0 docsity.com Summary Instruction encoding - Essential elements of computer instructions: type of operands, places of source and destinations and place of next instruction - Instruction word length Variable, fixed length and hybrid - Hybrid length taxonomy 4, 3, 2, 1 and 0 address format - Comparison of hybrid instruction word format Minimum number of memory bytes are required in case of 1 address (accumulator) format and maximum for 4-address format docsity.com Summary MIPS Instruction word format - RISC and MIPS is a fixed length, 64-bit LOAD/STORE Architecture - It supports: Size of Operand Character (8-bit) Half word (16-bit) Single precision FP or Word (32-bit) Double precision FP or double word (64-bit) - Instruction word formats R-type, I-type and J-type docsity.com Allah Hafiz
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