Download Amplifier Types-Introduction to Microelectronic Circuits-Lecture 25 Slides-Electrical Engineering and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 25, Slide 1EECS40, Fall 2003 Prof. King Lecture #25 Midterm #2 Information • Date: Monday November 3rd • Topics to be covered: – capacitors and inductors – 1st-order circuits (transient response) – semiconductor material properties – pn junctions & their applications – MOSFETs; common-source amplifier • Review session: Friday October 31st 2-4 PM OUTLINE – The transconductance amplifier (from Howe & Sodini Chapter 8.1) – Summary of MOSFET Lecture 25, Slide 2EECS40, Fall 2003 Prof. King 1. Voltage amplifier input & output signals are voltages 2. Current amplifier input and output signals are currents 3. Transconductance amplifier input signal is voltage; output signal is current 4. Transresistance amplifier input signal is current; output signal is voltage Amplifier Types amplifier + vin− + vout− amplifier ioutiin amplifier iout+ vin− amplifier iin + vout− 2 Lecture 25, Slide 3EECS40, Fall 2003 Prof. King Two-Port Amplifier Model for a transconductance amplifier gmvin Rout + vin − Rin iout Lecture 25, Slide 4EECS40, Fall 2003 Prof. King Effect of Source and Load Resistances • Overall transconductance is degraded by the source resistance Rs and load resistance RL gmvin Rout + vin − RLRin+–vs + + = outL out m sin in s out RR Rg RR R v i ioutRs 5 Lecture 25, Slide 9EECS40, Fall 2003 Prof. King PMOSFET I-V Equations “SATURATION” “LINEAR” or “TRIODE” DS DS TpGSpD V VVV L WkI −−′−= 2 ( )2 2 TpGS p DSAT VVL WkI − ′ −= vDS iD 0 |vGS| > |VTp| vDS = vGS–VT ≡ VDSAT Lecture 25, Slide 10EECS40, Fall 2003 Prof. King Channel-length modulation: • The length of the pinch-off region, ∆L, increases with increasing VDS above VGS–VT. It reduces the length of the inversion layer and hence the resistance of this layer. → iD increases noticeably with VDS, if L is small NMOSFET Summary: Non-Ideal Behavior vDS iD 0 cross-sectional view of channel: inversion layer VDSAT λ is the slope (channel-length modulation parameter) 6 Lecture 25, Slide 11EECS40, Fall 2003 Prof. King Velocity Saturation: • In a very-short-channel MOSFET, iD saturates because the carrier velocity is limited to ~107 cm/sec iD reaches a limit before pinch-off occurs (continued) < VGS–VTsat n DSAT sat DSAT TGSoxDSAT vLV vVVVWCI µ = −−= where 2 Lecture 25, Slide 12EECS40, Fall 2003 Prof. King (continued) Subthreshold Leakage: • For VGS ≤ VT, iD is exponentially dependent on VGS: • The leakage current specification sets the lower limit for the threshold voltage VT leakage current, IOFF vGS log iDS 0 VT 1/S is the slope 7 Lecture 25, Slide 13EECS40, Fall 2003 Prof. King NMOSFET Summary: Circuit Models • For analog circuit applications (where we are concerned only with changes in current and voltage signals, rather than their total values), the small-signal model is used: ( ) Do TGSnm Ig VVk L Wg λ≅ −′≅ gmvgs 1/go + vgs − id S D S G transconductance output conductance where VGS & ID are the DC bias (Q point) values Lecture 25, Slide 14EECS40, Fall 2003 Prof. King NMOSFET Summary: Circuit Models • For digital circuit applications, the MOSFET is modeled as a resistive switch: Req −≅ DDn DSATn DD eq VI VR λ 6 51 4 3 ( )2 2 TnDD n DSATn VVL WkI − ′ = vDS iD 0 VDDVDD/2 MOSFET is turned on (VGS = VDD) when VDS = VDD As the load capacitor discharges, VDS decreases to 0 V slope ≅ V DD / I DSAT slope ≅ VDD / 2 IDSAT
