Understanding Flip-Flops: Using Clocks to Control Memory in Digital Circuits, Study notes of Computer Architecture and Organization

Download Understanding Flip-Flops: Using Clocks to Control Memory in Digital Circuits and more Study notes Computer Architecture and Organization in PDF only on Docsity! Flip-flops 1 Flip-Flops • Last time, we saw how latches can be used as memory in a circuit. • Latches introduce new problems: – We need to know when to enable a latch. – We also need to quickly disable a latch. – In other words, it’s difficult to control the timing of latches in a large circuit. • We solve these problems with two new elements: clocks and flip-flops – Clocks tell us when to write to our memory. – Flip-flops allow us to quickly write the memory at clearly defined times. – Used together, we can create circuits without worrying about the memory timing. Flip-flops 2 An SR latch with a control input • Here is an SR latch with a control input C. • Notice the hierarchical design! – The dotted blue box is the S’R’ latch. – The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch. • The control input acts just like an enable. C S R S’ R’ Q 0 x x 1 1 No change 1 0 0 1 1 No change 1 0 1 1 0 0 (reset) 1 1 0 0 1 1 (set) 1 1 1 0 0 Avoid! Flip-flops 5 The problem with latches • The problem is exactly when to disable the latches. You have to wait long enough for the ALU to produce its output, but no longer. – But different ALU operations have different delays. For instance, arithmetic operations might go through an adder, whereas logical operations don’t. – Changing the ALU implementation, such as using a carry-lookahead adder instead of a ripple-carry adder, also affects the delay. • In general, it’s very difficult to know how long operations take, and how long latches should be enabled for. +1 ALU S X G Latches D Q C Flip-flops 6 Making latches work right • Our example used latches as memory for an ALU. – Let’s say there are four latches initially storing 0000. – We want to use an ALU to increment that value to 0001. • Normally the latches should be disabled, to prevent unwanted data from being accidentally stored. – In our example, the ALU can read the current latch contents, 0000, and compute their increment, 0001. – But the new value cannot be stored back while the latch is disabled. +1 ALU S X G Latches D Q C 0 0000 0001 Flip-flops 7 Writing to the latches • After the ALU has finished its increment operation, the latch can be enabled, and the updated value is stored. • The latch must be quickly disabled again, before the ALU has a chance to read the new value 0001 and produce a new result 0010. +1 ALU S X G Latches D Q C 1 0001 0001 +1 ALU S X G Latches D Q C 0 0001 0010 Flip-flops 10 More about clocks • Clocks are used extensively in computer architecture. • All processors run with an internal clock. – Modern chips run at frequencies up to 3.8 GHz. – This works out to a cycle time as little as 0.26 ns! • Memory modules are often rated by their clock speeds too—examples include “PC133” and “DDR400” memory. • Be careful...higher frequencies do not always mean faster machines! – You also have to consider how much work is actually being done during each clock cycle. – How much stuff can really get done in just 0.26 ns? – Take CS232. Flip-flops 11 Synchronizing our example • We can use a clock to synchronize our latches with the ALU. – The clock signal is connected to the latch control input C. – The clock controls the latches. When it becomes 1, the latches will be enabled for writing. • The clock period must be set appropriately for the ALU. – It should not be too short. Otherwise, the latches will start writing before the ALU operation has finished. – It should not be too long either. Otherwise, the ALU might produce a new result that will accidentally get stored, as we saw before. • The faster the ALU runs, the shorter the clock period can be. +1 ALU S X G Latches D Q C Flip-flops 12 • The second issue was how to enable a latch for just an instant. • Here is the internal structure of a D flip-flop. – The flip-flop inputs are C and D, and the outputs are Q and Q’. – The D latch on the left is the master, while the SR latch on the right is called the slave. • Note the layout here. – The flip-flop input D is connected directly to the master latch. – The master latch output goes to the slave. – The flip-flop outputs come directly from the slave latch. Flip-flops Flip-flops 15 Positive edge triggering • This is called a positive edge-triggered flip-flop. – The flip-flop output Q changes only after the positive edge of C. – The change is based on the flip-flop input values that were present right at the positive edge of the clock signal. • The D flip-flop’s behavior is similar to that of a D latch except for the positive edge-triggered nature, which is not explicit in this table. C D Q 0 x No change 1 0 0 (reset) 1 1 1 (set) Flip-flops 16 Direct inputs • One last thing to worry about… what is the starting value of Q? • We could set the initial value synchronously, at the next positive clock edge, but this actually makes circuit design more difficult. • Instead, most flip-flops provide direct, or asynchronous, inputs that let you immediately set or clear the state. – You would “reset” the circuit once, to initialize the flip-flops. – The circuit would then begin its regular, synchronous operation. • Here is a LogicWorks D flip-flop with active-low direct inputs. S’ R’ C D Q 0 0 x x Avoid! 0 1 x x 1 (set) 1 0 x x 0 (reset) 1 1 0 x No change 1 1 1 0 0 (reset) 1 1 1 1 1 (set) Direct inputs to set or reset the flip-flop S’R’ = 11 for “normal” operation of the D flip-flop Flip-flops 17 • We can use the flip-flops’ direct inputs to initialize them to 0000. • During the clock cycle, the ALU outputs 0001, but this does not affect the flip-flops yet. Our example with flip-flops +1 ALU S X G Flip-flops D Q C 0000 +1 ALU S X G Flip-flops D Q C 0000 0001 C Q0 G0 C Q0 G0 Flip-flops 20 Characteristic tables • The tables that we’ve made so far are called characteristic tables. – They show the next state Q(t+1) in terms of the current state Q(t) and the inputs. – For simplicity, the control input C is not usually listed. – Again, these tables don’t indicate the positive edge-triggered behavior of the flip-flops that we’ll be using. D Q(t+1) Operation 0 0 Reset 1 1 Set T Q(t+1) Operation 0 Q(t) No change 1 Q’(t) Complement J K Q(t+1) Operation 0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1 Q’(t) Complement Flip-flops 21 Characteristic equations • We can also write characteristic equations, where the next state Q(t+1) is defined in terms of the current state Q(t) and inputs. D Q(t+1) Operation 0 0 Reset 1 1 Set T Q(t+1) Operation 0 Q(t) No change 1 Q’(t) Complement J K Q(t+1) Operation 0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1 Q’(t) Complement Q(t+1) = D Q(t+1) = K’Q(t) + JQ’(t) Q(t+1) = T’Q(t) + TQ’(t) = T ⊕ Q(t) Flip-flops 22 Flip flop timing diagrams • “Present state” and “next state” are relative terms. • In the example JK flip-flop timing diagram on the left, you can see that at the first positive clock edge, J=1, K=1 and Q(1) = 1. • We can use this information to find the “next” state, Q(2) = Q(1)’. • Q(2) appears right after the first positive clock edge, as shown on the right. It will not change again until after the second clock edge. C J K Q 1 2 3 4 These values at clock cycle 1... C J K Q 1 2 3 4 … determine the “next” Q