Download Exam Questions for Electrical & Electronic Engineering Students: Unit 64EE1102 - Analogue and more Exams Electrical Engineering in PDF only on Docsity! S312 20/08/02 TH E MANCH ESTER M ETR O PO LITAN UNIVER SITY FACULTY O F SCIENCE AND ENGINEER ING D EPA R TMENT O F ENGINEER ING AND TECH NO LO GY SESSIO N 2001/2002 Exam ination for th e BEng (H O NS) ELECTR ICA L AND ELECTR O NIC ENGINEER ING H ND ELECTR O NIC ENGINEER ING YEA R O NE UNIT 64EE1102 : ANALO GUE ELECTR O NICS Th ursday 9 M ay 2002 2.00 pm to 4.00 pm Instructions to Candidates A ttem pt FO UR questions. Mark s for sections of questions are sh ow n in parenth eses. 20/08/02 continued 1 1. (a) A com m on em itter transistor am plifier h as b e en designed using an NPN b ipolar transistor. Th e am plifier uses base potentiom eter and em itter resistor b iasing in w h ich th e em itter resistor is NO T d ecoupled by a capacitor. From first principles and using h -param eters, derive an expression for th e sm all signal voltage gain of th e am plifier. A ssum e h oe is so sm all th at it can b e neglected. Your answ er sh ould include a circuit diagram and a sm all signal e quivalent circuit. [14] (b) D e sign a circuit of th e configuration describ ed in part (a) using th e follow ing inform ation: VCC = 10 V h fe = 100 ICQ = 0.5m A VCQ = 5 V Use th e nearest preferred value (NPV) for resistors in your design. [11] 2. (a) Th e output stage of a pow er am plifier dissipates 50 W . It com prises tw o identical transistors w ith θJC = 1.5 °C/W . Th ey are both bolted onto one h eatsink . If th e m axim um perm issible transistor junction tem perature is 150 °C and th e m axim um am b ient tem perature is 50 °C: (i) w h at m ust th e m axim um th erm al resistance of th e h eatsink , θCA , b e? [6] (ii) w h at is th e m axim um tem perature of th e h eatsink ? [5] (b) Th e th erm al resistance, θCA , of th e b e st available h eatsink for th e am plifier describ ed above is 2 °C/W . Fan cooling is th erefore used w h ich effectively reduces θCA to 0.7 °C/W . (i) W h at w ould be th e junction tem perature now ? [6] (ii) A pproxim ately by w h at percentage can th e pow er output b e increased before th e m axim um junction tem perature is reach ed? [8] 20/08/02 continued 4 4. (a) Explain w h at is m eant by th e term ‘recom b ination’. [3] (b) Explain w h at is m eant by a p-n junction. [3] (c) Explain w ith th e aid of a diagram w h at is m eant by an ab rupt p-n junction. [3] (d) D e scrib e b riefly w ith th e aid of diagram s th e operation of an isolated p-n junction. [6] (e) Explain w h at is m eant by th e term ‘contact potential’. [2] (f) Explain th e operation of a forw ard biased p-n junction. [8] 5. Th e fabrication of sem iconductor devices requires th e use of silicon oxide and th e introduction of donor or acceptor im purities into th e intrinsic sem iconductor to produce extrinsic m aterial. (a) D escrib e b riefly h ow silicon oxide is produced. [3] (b) Explain th e m eaning of th e term ‘Epitaxy’. [2] (c) Explain th e m eaning of th e term ‘Ion im plantation’. [2] (d) Explain th e m eaning of th e term ‘D e position’. [2] (e) Explain w h y MA SKS are needed to m anufacture electronic devices. [2] (f) W h at m aterials are used to m ak e th e m ask s? [2] (g) D e scrib e w ith th e aid of diagram s h ow an MO S transistor is fab ricated. O n th e diagram s indicate w h ere th e follow ing sub stances occur • Ph oto-resist • Silicon O xide • Polysilicon • D iffusion • Substrate [12] 5 S312 20/08/02 6. (a) D raw th e circuit diagram of a com plim entary MO S inverter. [5] (b) D e scrib e th e m ode th e n-type and p-type devices are operating in w h en 0 = Vin = Vtn. [5] (c) D e scrib e th e m ode th e n-type and p-type devices are operating in w h en Vtn = Vin = Vdd/2. [5] (d) D raw a graph of th e overall ch aracteristics of th e MO S inverter. [5] (e) Sh ow h ow th e ch aracteristics of th e MO S inverter are affected by ch anges in th e ratio of βn/βp. [5] END