Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Digital Logic Terms: Clocking, Systems, Flip-Flops, Latches, D Flip-Flops, Setup/Hold Time, Quizzes of Computer Architecture and Organization

Definitions for various terms related to digital logic, including edge triggered clocking, synchronous systems, flip-flops, latches, d flip-flops, setup time, hold time, combinational logic, sequential logic, gates, decoders, selector value, sum of products, programmable logic array, minterms, read-only memory (rom), programmable rom (prom), bus, and clock skew.

Typology: Quizzes

2010/2011

Uploaded on 04/01/2011

olofguard
olofguard 🇺🇸

17 documents

1 / 4

Toggle sidebar

Related documents


Partial preview of the text

Download Digital Logic Terms: Clocking, Systems, Flip-Flops, Latches, D Flip-Flops, Setup/Hold Time and more Quizzes Computer Architecture and Organization in PDF only on Docsity! TERM 1 Edge Triggered Clocking DEFINITION 1 A clocking scheme in which all state changes occur on a clock edge. TERM 2 synchronous system DEFINITION 2 A memory system that employs clocks and where data signals are read only when the clock indicates that the signal values are stable. TERM 3 flip-flop DEFINITION 3 A memory element for which the output is equal to the value of the stored state inside the element and for which the internal state is changed only on a clock edge. TERM 4 latch DEFINITION 4 A memory element in which the output is equal to the value of the stored state inside the element and the state is changed whenever the appropriate inputs change and the clock is asserted. TERM 5 D flip- flop DEFINITION 5 A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs. TERM 6 setup time DEFINITION 6 The minimum time that the input to a memory device must be valid before the clock edge. TERM 7 hold time DEFINITION 7 The minimum time during which the input must be valid after the clock edge. TERM 8 combinational logic DEFINITION 8 A logicsystem whose blocks do notcontain memory and hencecompute the same output giventhe same input. TERM 9 sequential logic DEFINITION 9 A group oflogic elements that containmemory and hence whose valuedepends on the inputs as well asthe current contents of thememory. TERM 10 gate DEFINITION 10 A device that implementsbasic logic functions, such asAND or OR.
Docsity logo



Copyright © 2024 Ladybird Srl - Via Leonardo da Vinci 16, 10126, Torino, Italy - VAT 10816460017 - All rights reserved