Architecture for Programmers Volume II - Introduction to the MIPS 32 Architecture | CS 1541, Papers of Computer Science

Download Architecture for Programmers Volume II - Introduction to the MIPS 32 Architecture | CS 1541 and more Papers Computer Science in PDF only on Docsity! Document Number: MD00086 Revision 2.00 June 9, 2003 MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043-1353 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. MIPS32™ Architecture For Programmers Volume II: The MIPS32™ Instruction Set Copyright © 2001-2003 MIPS Technologies, Inc. All rights reserved. Unpublished rights (if any) are reserved under the Copyright Laws of the United States of America. If this document is provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format), then its use and distribution is subject to a written agreement with MIPS Technologies, Inc. ("MIPS Technologies"). UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY WITHOUT THE EXPRESS WRITTEN CONSENT OF MIPS TECHNOLOGIES. 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MADDU ............................................................................................................................................................................................................................ 175 MFC0 ................................................................................................................................................................................................................................. 176 MFC1 ................................................................................................................................................................................................................................. 177 MFC2 ................................................................................................................................................................................................................................. 178 MFHC1 .............................................................................................................................................................................................................................. 179 MFHC2 .............................................................................................................................................................................................................................. 180 MFHI.................................................................................................................................................................................................................................. 181 MFLO ................................................................................................................................................................................................................................ 182 MOV.fmt............................................................................................................................................................................................................................ 183 MOVF................................................................................................................................................................................................................................ 184 MOVF.fmt ......................................................................................................................................................................................................................... 185 MOVN ............................................................................................................................................................................................................................... 187 MOVN.fmt......................................................................................................................................................................................................................... 188 MOVT................................................................................................................................................................................................................................ 190 MOVT.fmt ......................................................................................................................................................................................................................... 191 MOVZ................................................................................................................................................................................................................................ 193 MOVZ.fmt ......................................................................................................................................................................................................................... 194 MSUB ................................................................................................................................................................................................................................ 196 MSUB.fmt.......................................................................................................................................................................................................................... 197 MSUBU ............................................................................................................................................................................................................................. 199 MTC0................................................................................................................................................................................................................................. 200 MTC1................................................................................................................................................................................................................................. 201 MTC2................................................................................................................................................................................................................................. 202 MTHC1.............................................................................................................................................................................................................................. 203 MTHC2.............................................................................................................................................................................................................................. 204 MTHI ................................................................................................................................................................................................................................. 205 MTLO ................................................................................................................................................................................................................................ 206 MUL................................................................................................................................................................................................................................... 207 MUL.fmt ............................................................................................................................................................................................................................ 208 MULT ................................................................................................................................................................................................................................ 209 MULTU ............................................................................................................................................................................................................................. 210 NEG.fmt............................................................................................................................................................................................................................. 211 NMADD.fmt...................................................................................................................................................................................................................... 212 NMSUB.fmt....................................................................................................................................................................................................................... 214 NOP.................................................................................................................................................................................................................................... 216 NOR ................................................................................................................................................................................................................................... 217 OR...................................................................................................................................................................................................................................... 218 ORI..................................................................................................................................................................................................................................... 219 PLL.PS............................................................................................................................................................................................................................... 220 PLU.PS .............................................................................................................................................................................................................................. 221 PREF.................................................................................................................................................................................................................................. 222 PREFX ............................................................................................................................................................................................................................... 226 PUL.PS .............................................................................................................................................................................................................................. 227 PUU.PS .............................................................................................................................................................................................................................. 228 RDHWR............................................................................................................................................................................................................................. 229 RDPGPR............................................................................................................................................................................................................................ 231 RECIP.fmt.......................................................................................................................................................................................................................... 232 ROTR................................................................................................................................................................................................................................. 234 ROTRV.............................................................................................................................................................................................................................. 235 ROUND.L.fmt ................................................................................................................................................................................................................... 236 ROUND.W.fmt .................................................................................................................................................................................................................. 238 RSQRT.fmt ........................................................................................................................................................................................................................ 240 SB....................................................................................................................................................................................................................................... 242 SC....................................................................................................................................................................................................................................... 243 SDBBP............................................................................................................................................................................................................................... 246 SDC1.................................................................................................................................................................................................................................. 247 SDC2.................................................................................................................................................................................................................................. 248 SDXC1............................................................................................................................................................................................................................... 249 SEB .................................................................................................................................................................................................................................... 250 SEH.................................................................................................................................................................................................................................... 251 SH ...................................................................................................................................................................................................................................... 253 SLL .................................................................................................................................................................................................................................... 254 SLLV.................................................................................................................................................................................................................................. 255 SLT .................................................................................................................................................................................................................................... 256 SLTI ................................................................................................................................................................................................................................... 257 SLTIU ................................................................................................................................................................................................................................ 258MIPS32™ Architecture For Programmers Volume II, Revision 2.00 iii Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. SLTU.................................................................................................................................................................................................................................. 259 SQRT.fmt........................................................................................................................................................................................................................... 260 SRA.................................................................................................................................................................................................................................... 261 SRAV................................................................................................................................................................................................................................. 262 SRL .................................................................................................................................................................................................................................... 263 SRLV ................................................................................................................................................................................................................................. 264 SSNOP ............................................................................................................................................................................................................................... 265 SUB.................................................................................................................................................................................................................................... 266 SUB.fmt ............................................................................................................................................................................................................................. 267 SUBU................................................................................................................................................................................................................................. 268 SUXC1............................................................................................................................................................................................................................... 269 SW...................................................................................................................................................................................................................................... 270 SWC1................................................................................................................................................................................................................................. 271 SWC2................................................................................................................................................................................................................................. 272 SWL ................................................................................................................................................................................................................................... 273 SWR................................................................................................................................................................................................................................... 275 SWXC1.............................................................................................................................................................................................................................. 277 SYNC................................................................................................................................................................................................................................. 278 SYNCI................................................................................................................................................................................................................................ 282 SYSCALL.......................................................................................................................................................................................................................... 285 TEQ.................................................................................................................................................................................................................................... 286 TEQI .................................................................................................................................................................................................................................. 287 TGE.................................................................................................................................................................................................................................... 288 TGEI .................................................................................................................................................................................................................................. 289 TGEIU................................................................................................................................................................................................................................ 290 TGEU................................................................................................................................................................................................................................. 291 TLBP.................................................................................................................................................................................................................................. 292 TLBR ................................................................................................................................................................................................................................. 293 TLBWI............................................................................................................................................................................................................................... 295 TLBWR.............................................................................................................................................................................................................................. 297 TLT .................................................................................................................................................................................................................................... 299 TLTI................................................................................................................................................................................................................................... 300 TLTIU................................................................................................................................................................................................................................ 301 TLTU ................................................................................................................................................................................................................................. 302 TNE.................................................................................................................................................................................................................................... 303 TNEI .................................................................................................................................................................................................................................. 304 TRUNC.L.fmt .................................................................................................................................................................................................................... 305 TRUNC.W.fmt................................................................................................................................................................................................................... 307 WAIT ................................................................................................................................................................................................................................. 309 WRPGPR ........................................................................................................................................................................................................................... 311 WSBH................................................................................................................................................................................................................................ 312 XOR ................................................................................................................................................................................................................................... 313 XORI.................................................................................................................................................................................................................................. 314 Appendix A Instruction Bit Encodings ................................................................................................................................... 315 A.1 Instruction Encodings and Instruction Classes ......................................................................................................... 315 A.2 Instruction Bit Encoding Tables................................................................................................................................ 315 A.3 Floating Point Unit Instruction Format Encodings ................................................................................................... 322 Appendix B Revision History ................................................................................................................................................. 325iv MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. MIPS32™ Architecture For Programmers Volume II, Revision 2.00 v Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. List of Figures Figure 2-1: Example of Instruction Description .......................................................................................................................... 8 Figure 2-2: Example of Instruction Fields ................................................................................................................................... 9 Figure 2-3: Example of Instruction Descriptive Name and Mnemonic ....................................................................................... 9 Figure 2-4: Example of Instruction Format.................................................................................................................................. 9 Figure 2-5: Example of Instruction Purpose .............................................................................................................................. 10 Figure 2-6: Example of Instruction Description ........................................................................................................................ 10 Figure 2-7: Example of Instruction Restrictions ........................................................................................................................ 11 Figure 2-8: Example of Instruction Operation ........................................................................................................................... 11 Figure 2-9: Example of Instruction Exception........................................................................................................................... 11 Figure 2-10: Example of Instruction Programming Notes......................................................................................................... 12 Figure 2-11: COP_LW Pseudocode Function............................................................................................................................ 13 Figure 2-12: COP_LD Pseudocode Function............................................................................................................................. 13 Figure 2-13: COP_SW Pseudocode Function............................................................................................................................ 13 Figure 2-14: COP_SD Pseudocode Function............................................................................................................................. 14 Figure 2-15: AddressTranslation Pseudocode Function ............................................................................................................ 14 Figure 2-16: LoadMemory Pseudocode Function...................................................................................................................... 15 Figure 2-17: StoreMemory Pseudocode Function ..................................................................................................................... 15 Figure 2-18: Prefetch Pseudocode Function .............................................................................................................................. 16 Figure 2-19: ValueFPR Pseudocode Function ........................................................................................................................... 17 Figure 2-20: StoreFPR Pseudocode Function ............................................................................................................................ 18 Figure 2-21: SyncOperation Pseudocode Function.................................................................................................................... 18 Figure 2-22: SignalException Pseudocode Function ................................................................................................................. 18 Figure 2-23: SignalDebugBreakpointException Pseudocode Function..................................................................................... 19 Figure 2-24: SignalDebugModeBreakpointException Pseudocode Function ........................................................................... 19 Figure 2-25: NullifyCurrentInstruction PseudoCode Function.................................................................................................. 19 Figure 2-26: CoprocessorOperation Pseudocode Function........................................................................................................ 19 Figure 2-27: JumpDelaySlot Pseudocode Function ................................................................................................................... 20 Figure 2-28: FPConditionCode Pseudocode Function............................................................................................................... 20 Figure 2-29: SetFPConditionCode Pseudocode Function.......................................................................................................... 20 Figure 3-1: Example of an ALNV.PS Operation ....................................................................................................................... 39 Figure 3-2: Usage of Address Fields to Select Index and Way ................................................................................................. 91 Figure 3-3: Operation of the EXT Instruction.......................................................................................................................... 131 Figure 3-4: Operation of the INS Instruction ........................................................................................................................... 136 Figure 3-5: Unaligned Word Load Using LWL and LWR ...................................................................................................... 164 Figure 3-6: Bytes Loaded by LWL Instruction........................................................................................................................ 165 Figure 3-7: Unaligned Word Load Using LWL and LWR ...................................................................................................... 168 Figure 3-8: Bytes Loaded by LWL Instruction........................................................................................................................ 169 Figure 3-9: Unaligned Word Store Using SWL and SWR ...................................................................................................... 273 Figure 3-10: Bytes Stored by an SWL Instruction................................................................................................................... 274 Figure 3-11: Unaligned Word Store Using SWR and SWL .................................................................................................... 275 Figure 3-12: Bytes Stored by SWR Instruction ....................................................................................................................... 276 Figure A-1: Sample Bit Encoding Table.................................................................................................................................. 316 viii MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 1 About This Book The MIPS32™ Architecture For Programmers Volume II comes as a multi-volume set. • Volume I describes conventions used throughout the document set, and provides an introduction to the MIPS32™ Architecture • Volume II provides detailed descriptions of each instruction in the MIPS32™ instruction set • Volume III describes the MIPS32™ Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32™ processor implementation • Volume IV-a describes the MIPS16e™ Application-Specific Extension to the MIPS32™ Architecture • Volume IV-b describes the MDMX™ Application-Specific Extension to the MIPS32™ Architecture and is not applicable to the MIPS32™ document set • Volume IV-c describes the MIPS-3D™ Application-Specific Extension to the MIPS64™ Architecture and is not applicable to the MIPS32™ document set • Volume IV-d describes the SmartMIPS™Application-Specific Extension to the MIPS32™ Architecture 1.1 Typographical Conventions This section describes the use of italic, bold and courier fonts in this book. 1.1.1 Italic Text • is used for emphasis • is used for bits, fields, registers, that are important from a software perspective (for instance, address bits used by software, and programmable fields and registers), and various floating point instruction formats, such as S, D, and PS • is used for the memory access types, such as cached and uncached 1.1.2 Bold Text • represents a term that is being defined • is used for bits and fields that are important from a hardware perspective (for instance, register bits, which are not programmable but accessible only to hardware) • is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through 1 • is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below. 1.1.3 Courier Text Courier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.MIPS32™ Architecture For Programmers Volume II, Revision 2.00 1 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 1 About This Book1.2 UNPREDICTABLE and UNDEFINED The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations. 1.2.1 UNPREDICTABLE UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is generated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions. UNPREDICTABLE results or operations have several implementation restrictions: • Implementations of operations generating UNPREDICTABLE results must not depend on any data source (memory or internal state) which is inaccessible in the current processor mode • UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process • UNPREDICTABLE operations must not halt or hang the processor 1.2.2 UNDEFINED UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED operations or behavior may cause data loss. UNDEFINED operations or behavior has one implementation restriction: • UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which there is no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state 1.3 Special Symbols in Pseudocode Notation In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1. Table 1-1 Symbols Used in Instruction Operation Statements Symbol Meaning ← Assignment =, ≠ Tests for equality and inequality || Bit string concatenation xy A y-bit string formed by y copies of the single-bit value x2 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 1.4 For More InformationComments or questions on the MIPS32™ Architecture or this document should be directed to Director of MIPS Architecture MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043 or via E-mail to architecture@mips.com.MIPS32™ Architecture For Programmers Volume II, Revision 2.00 5 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 1 About This Book6 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction Set This chapter provides a detailed guide to understanding the instruction descriptions, which are listed in alphabetical order in the tables at the beginning of the next chapter. 2.1 Understanding the Instruction Fields Figure 2-1 shows an example instruction. Following the figure are descriptions of the fields listed below: • “Instruction Fields” on page 8 • “Instruction Descriptive Name and Mnemonic” on page 9 • “Format Field” on page 9 • “Purpose Field” on page 10 • “Description Field” on page 10 • “Restrictions Field” on page 10 • “Operation Field” on page 11 • “Exceptions Field” on page 11 • “Programming Notes and Implementation Notes Fields” on page 11MIPS32™ Architecture For Programmers Volume II, Revision 2.00 7 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction SetThe assembler format lines sometimes include parenthetical comments to help explain variations in the formats (once again, see C.cond.fmt). These comments are not a part of the assembler format. 2.1.4 Purpose Field The Purpose field gives a short description of the use of the instruction. Purpose: To add 32-bit integers. If an overflow occurs, then trap. Figure 2-5 Example of Instruction Purpose 2.1.5 Description Field If a one-line symbolic description of the instruction is feasible, it appears immediately to the right of the Description heading. The main purpose is to show how fields in the instruction are used in the arithmetic or logical operation. Description: rd ← rs + rt The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result. • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs • If the addition does not overflow, the 32-bit result is placed into GPR rd Figure 2-6 Example of Instruction Description The body of the section is a description of the operation of the instruction in text, tables, and figures. This description complements the high-level language description in the Operation section. This section uses acronyms for register descriptions. “GPR rt” is CPU general-purpose register specified by the instruction field rt. “FPR fs” is the floating point operand register specified by the instruction field fs. “CP1 register fd” is the coprocessor 1 general register specified by the instruction field fd. “FCSR” is the floating point Control /Status register. 2.1.6 Restrictions Field The Restrictions field documents any possible restrictions that may affect the instruction. Most restrictions fall into one of the following six categories: • Valid values for instruction fields (for example, see floating point ADD.fmt) • ALIGNMENT requirements for memory addresses (for example, see LW) • Valid values of operands (for example, see DADD) • Valid operand formats (for example, see floating point ADD.fmt) • Order of instructions necessary to guarantee correct execution. These ordering constraints avoid pipeline hazards for which some processors do not have hardware interlocks (for example, see MUL). • Valid memory access types (for example, see LL/SC)10 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 2.1 Understanding the Instruction FieldsRestrictions: None Figure 2-7 Example of Instruction Restrictions 2.1.7 Operation Field The Operation field describes the operation of the instruction as pseudocode in a high-level language notation resembling Pascal. This formal description complements the Description section; it is not complete in itself because many of the restrictions are either difficult to include in the pseudocode or are omitted for legibility. Operation: temp ← (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then SignalException(IntegerOverflow) else GPR[rd] ← temp endif Figure 2-8 Example of Instruction Operation See Section 2.2, "Operation Section Notation and Functions" on page 12 for more information on the formal notation used here. 2.1.8 Exceptions Field The Exceptions field lists the exceptions that can be caused by Operation of the instruction. It omits exceptions that can be caused by the instruction fetch, for instance, TLB Refill, and also omits exceptions that can be caused by asynchronous external events such as an Interrupt. Although a Bus Error exception may be caused by the operation of a load or store instruction, this section does not list Bus Error for load and store instructions because the relationship between load and store instructions and external error indications, like Bus Error, are dependent upon the implementation. Exceptions: Integer Overflow Figure 2-9 Example of Instruction Exception An instruction may cause implementation-dependent exceptions that are not present in the Exceptions section. 2.1.9 Programming Notes and Implementation Notes FieldsMIPS32™ Architecture For Programmers Volume II, Revision 2.00 11 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction SetThe Notes sections contain material that is useful for programmers and implementors, respectively, but that is not necessary to describe the instruction and does not belong in the description sections. Programming Notes: ADDU performs the same arithmetic operation but does not trap on overflow. Figure 2-10 Example of Instruction Programming Notes 2.2 Operation Section Notation and Functions In an instruction description, the Operation section uses a high-level language notation to describe the operation performed by each instruction. Special symbols used in the pseudocode are described in the previous chapter. Specific pseudocode functions are described below. This section presents information about the following topics: • “Instruction Execution Ordering” on page 12 • “Pseudocode Functions” on page 12 2.2.1 Instruction Execution Ordering Each of the high-level language statements in the Operations section are executed sequentially (except as constrained by conditional and loop constructs). 2.2.2 Pseudocode Functions There are several functions used in the pseudocode descriptions. These are used either to make the pseudocode more readable, to abstract implementation-specific behavior, or both. These functions are defined in this section, and include the following: • “Coprocessor General Register Access Functions” on page 12 • “Load Memory and Store Memory Functions” on page 14 • “Access Functions for Floating Point Registers” on page 16 • “Miscellaneous Functions” on page 18 2.2.2.1 Coprocessor General Register Access Functions Defined coprocessors, except for CP0, have instructions to exchange words and doublewords between coprocessor general registers and the rest of the system. What a coprocessor does with a word or doubleword supplied to it and how a coprocessor supplies a word or doubleword is defined by the coprocessor itself. This behavior is abstracted into the functions described in this section. COP_LW The COP_LW function defines the action taken by coprocessor z when supplied with a word from memory during a load word operation. The action is coprocessor-specific. The typical action would be to store the contents of memword in coprocessor general register rt.12 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 2.2 Operation Section Notation and FunctionsMemElem ← LoadMemory (CCA, AccessLength, pAddr, vAddr, IorD) /* MemElem: Data is returned in a fixed width with a natural alignment. The */ /* width is the same size as the CPU general-purpose register, */ /* 32 or 64 bits, aligned on a 32- or 64-bit boundary, */ /* respectively. */ /* CCA: Cache Coherence Algorithm, the method used to access caches */ /* and memory and resolve the reference */ /* AccessLength: Length, in bytes, of access */ /* pAddr: physical address */ /* vAddr: virtual address */ /* IorD: Indicates whether access is for Instructions or Data */ endfunction LoadMemory Figure 2-16 LoadMemory Pseudocode Function StoreMemory The StoreMemory function stores a value to memory. The specified data is stored into the physical location pAddr using the memory hierarchy (data caches and main memory) as specified by the Cache Coherence Algorithm (CCA). The MemElem contains the data for an aligned, fixed-width memory element (a word for 32-bit processors, a doubleword for 64-bit processors), though only the bytes that are actually stored to memory need be valid. The low-order two (or three) bits of pAddr and the AccessLength field indicate which of the bytes within the MemElem data should be stored; only these bytes in memory will actually be changed. StoreMemory (CCA, AccessLength, MemElem, pAddr, vAddr) /* CCA: Cache Coherence Algorithm, the method used to access */ /* caches and memory and resolve the reference. */ /* AccessLength: Length, in bytes, of access */ /* MemElem: Data in the width and alignment of a memory element. */ /* The width is the same size as the CPU general */ /* purpose register, either 4 or 8 bytes, */ /* aligned on a 4- or 8-byte boundary. For a */ /* partial-memory-element store, only the bytes that will be*/ /* stored must be valid.*/ /* pAddr: physical address */ /* vAddr: virtual address */ endfunction StoreMemory Figure 2-17 StoreMemory Pseudocode Function Prefetch The Prefetch function prefetches data from memory. Prefetch is an advisory instruction for which an implementation-specific action is taken. The action taken may increase performance but must not change the meaning of the program or alter architecturally visible state. Prefetch (CCA, pAddr, vAddr, DATA, hint) /* CCA: Cache Coherence Algorithm, the method used to access */ /* caches and memory and resolve the reference. */ /* pAddr: physical address */MIPS32™ Architecture For Programmers Volume II, Revision 2.00 15 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction Set/* vAddr: virtual address */ /* DATA: Indicates that access is for DATA */ /* hint: hint that indicates the possible use of the data */ endfunction Prefetch Figure 2-18 Prefetch Pseudocode Function Table 2-1 lists the data access lengths and their labels for loads and stores. 2.2.2.3 Access Functions for Floating Point Registers The pseudocode shown in below specifies how the unformatted contents loaded or moved to CP1 registers are interpreted to form a formatted value. If an FPR contains a value in some format, rather than unformatted contents from a load (uninterpreted), it is valid to interpret the value in that format (but not to interpret it in a different format). ValueFPR The ValueFPR function returns a formatted value from the floating point registers. value ← ValueFPR(fpr, fmt) /* value: The formattted value from the FPR */ /* fpr: The FPR number */ /* fmt: The format of the data, one of: */ /* S, D, W, L, PS, */ /* OB, QH, */ /* UNINTERPRETED_WORD, */ /* UNINTERPRETED_DOUBLEWORD */ /* The UNINTERPRETED values are used to indicate that the datatype */ /* is not known as, for example, in SWC1 and SDC1 */ case fmt of S, W, UNINTERPRETED_WORD: valueFPR ← FPR[fpr] D, UNINTERPRETED_DOUBLEWORD: if (FP32RegistersMode = 0) if (fpr0 ≠ 0) then valueFPR ← UNPREDICTABLE Table 2-1 AccessLength Specifications for Loads/Stores AccessLength Name Value Meaning DOUBLEWORD 7 8 bytes (64 bits) SEPTIBYTE 6 7 bytes (56 bits) SEXTIBYTE 5 6 bytes (48 bits) QUINTIBYTE 4 5 bytes (40 bits) WORD 3 4 bytes (32 bits) TRIPLEBYTE 2 3 bytes (24 bits) HALFWORD 1 2 bytes (16 bits) BYTE 0 1 byte (8 bits)16 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 2.2 Operation Section Notation and Functionselse valueFPR ← FPR[fpr+1]31..0 || FPR[fpr]31..0 endif else valueFPR ← FPR[fpr] endif L, PS: if (FP32RegistersMode = 0) then valueFPR ← UNPREDICTABLE else valueFPR ← FPR[fpr] endif DEFAULT: valueFPR ← UNPREDICTABLE endcase endfunction ValueFPR Figure 2-19 ValueFPR Pseudocode Function StoreFPR The pseudocode shown below specifies the way a binary encoding representing a formatted value is stored into CP1 registers by a computational or move operation. This binary representation is visible to store or move-from instructions. Once an FPR receives a value from the StoreFPR(), it is not valid to interpret the value with ValueFPR() in a different format. StoreFPR (fpr, fmt, value) /* fpr: The FPR number */ /* fmt: The format of the data, one of: */ /* S, D, W, L, PS, */ /* OB, QH, */ /* UNINTERPRETED_WORD, */ /* UNINTERPRETED_DOUBLEWORD */ /* value: The formattted value to be stored into the FPR */ /* The UNINTERPRETED values are used to indicate that the datatype */ /* is not known as, for example, in LWC1 and LDC1 */ case fmt of S, W, UNINTERPRETED_WORD: FPR[fpr] ← value D, UNINTERPRETED_DOUBLEWORD: if (FP32RegistersMode = 0) if (fpr0 ≠ 0) then UNPREDICTABLE else FPR[fpr] ← UNPREDICTABLE32 || value31..0 FPR[fpr+1] ← UNPREDICTABLE32 || value63..32 endif else FPR[fpr] ← value endifMIPS32™ Architecture For Programmers Volume II, Revision 2.00 17 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction Set/* vAddr:Virtual address */ endfunction JumpDelaySlot Figure 2-27 JumpDelaySlot Pseudocode Function FPConditionCode The FPConditionCode function returns the value of a specific floating point condition code. tf ←FPConditionCode(cc) /* tf: The value of the specified condition code */ /* cc: The Condition code number in the range 0..7 */ if cc = 0 then FPConditionCode ← FCSR23 else FPConditionCode ← FCSR24+cc endif endfunction FPConditionCode Figure 2-28 FPConditionCode Pseudocode Function SetFPConditionCode The SetFPConditionCode function writes a new value to a specific floating point condition code. SetFPConditionCode(cc) if cc = 0 then FCSR ← FCSR31..24 || tf || FCSR22..0 else FCSR ← FCSR31..25+cc || tf || FCSR23+cc..0 endif endfunction SetFPConditionCode Figure 2-29 SetFPConditionCode Pseudocode Function 2.3 Op and Function Subfield Notation In some instructions, the instruction subfields op and function can have constant 5- or 6-bit values. When reference is made to these instructions, uppercase mnemonics are used. For instance, in the floating point ADD instruction, op=COP1 and function=ADD. In other cases, a single field has both fixed and variable subfields, so the name contains both upper- and lowercase characters. 2.4 FPU Instructions In the detailed description of each FPU instruction, all variable subfields in an instruction format (such as fs, ft, immediate, and so on) are shown in lowercase. The instruction name (such as ADD, SUB, and so on) is shown in uppercase.20 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 2.4 FPU InstructionsFor the sake of clarity, an alias is sometimes used for a variable subfield in the formats of specific instructions. For example, rs=base in the format for load and store instructions. Such an alias is always lowercase since it refers to a variable subfield. Bit encodings for mnemonics are given in Volume I, in the chapters describing the CPU, FPU, MDMX, and MIPS16e instructions. See Section 2.3, "Op and Function Subfield Notation" on page 20 for a description of the op and function subfields.MIPS32™ Architecture For Programmers Volume II, Revision 2.00 21 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 2 Guide to the Instruction Set22 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 3.2 Alphabetical List of InstructionsBAL Branch and Link BEQ Branch on Equal BGEZ Branch on Greater Than or Equal to Zero BGEZAL Branch on Greater Than or Equal to Zero and Link BGTZ Branch on Greater Than Zero BLEZ Branch on Less Than or Equal to Zero BLTZ Branch on Less Than Zero BLTZAL Branch on Less Than Zero and Link BNE Branch on Not Equal J Jump JAL Jump and Link JALR Jump and Link Register JALR.HB Jump and Link Register with Hazard Barrier Release 2 Only JR Jump Register JR.HB Jump Register with Hazard Barrier Release 2 Only Table 3-3 CPU Instruction Control Instructions Mnemonic Instruction EHB Execution Hazard Barrier Release 2 Only NOP No Operation SSNOP Superscalar No Operation Table 3-4 CPU Load, Store, and Memory Control Instructions Mnemonic Instruction LB Load Byte LBU Load Byte Unsigned LH Load Halfword LHU Load Halfword Unsigned LL Load Linked Word LW Load Word LWL Load Word Left LWR Load Word Right PREF Prefetch Table 3-2 CPU Branch and Jump Instructions Mnemonic InstructionMIPS32™ Architecture For Programmers Volume II, Revision 2.00 25 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 3 The MIPS32™ Instruction SetSB Store Byte SC Store Conditional Word SD Store Doubleword SH Store Halfword SW Store Word SWL Store Word Left SWR Store Word Right SYNC Synchronize Shared Memory SYNCI Synchronize Caches to Make Instruction Writes Effective Release 2 Only Table 3-5 CPU Logical Instructions Mnemonic Instruction AND And ANDI And Immediate LUI Load Upper Immediate NOR Not Or OR Or ORI Or Immediate XOR Exclusive Or XORI Exclusive Or Immediate Table 3-6 CPU Insert/Extract Instructions Mnemonic Instruction EXT Extract Bit Field Release 2 Only INS Insert Bit Field Release 2 Only WSBH Word Swap Bytes Within Halfwords Release 2 Only Table 3-7 CPU Move Instructions Mnemonic Instruction MFHI Move From HI Register MFLO Move From LO Register MOVF Move Conditional on Floating Point False Table 3-4 CPU Load, Store, and Memory Control Instructions Mnemonic Instruction26 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 3.2 Alphabetical List of InstructionsMOVN Move Conditional on Not Zero MOVT Move Conditional on Floating Point True MOVZ Move Conditional on Zero MTHI Move To HI Register MTLO Move To LO Register RDHWR Read Hardware Register Release 2 Only Table 3-8 CPU Shift Instructions Mnemonic Instruction ROTR Rotate Word Right Release 2 Only ROTRV Rotate Word Right Variable Release 2 Only SLL Shift Word Left Logical SLLV Shift Word Left Logical Variable SRA Shift Word Right Arithmetic SRAV Shift Word Right Arithmetic Variable SRL Shift Word Right Logical SRLV Shift Word Right Logical Variable Table 3-9 CPU Trap Instructions Mnemonic Instruction BREAK Breakpoint SYSCALL System Call TEQ Trap if Equal TEQI Trap if Equal Immediate TGE Trap if Greater or Equal TGEI Trap if Greater of Equal Immediate TGEIU Trap if Greater or Equal Immediate Unsigned TGEU Trap if Greater or Equal Unsigned TLT Trap if Less Than TLTI Trap if Less Than Immediate TLTIU Trap if Less Than Immediate Unsigned TLTU Trap if Less Than Unsigned TNE Trap if Not Equal Table 3-7 CPU Move Instructions Mnemonic InstructionMIPS32™ Architecture For Programmers Volume II, Revision 2.00 27 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 3 The MIPS32™ Instruction SetTable 3-15 FPU Load, Store, and Memory Control Instructions Mnemonic Instruction LDC1 Load Doubleword to Floating Point LDXC1 Load Doubleword Indexed to Floating Point 64-bit FPU Only LUXC1 Load Doubleword Indexed Unaligned to Floating Point 64-bit FPU Only LWC1 Load Word to Floating Point LWXC1 Load Word Indexed to Floating Point 64-bit FPU Only PREFX Prefetch Indexed SDC1 Store Doubleword from Floating Point SDXC1 Store Doubleword Indexed from Floating Point 64-bit FPU Only SUXC1 Store Doubleword Indexed Unaligned from Floating Point 64-bit FPU Only SWC1 Store Word from Floating Point SWXC1 Store Word Indexed from Floating Point 64-bit FPU Only Table 3-16 FPU Move Instructions Mnemonic Instruction CFC1 Move Control Word from Floating Point CTC1 Move Control Word to Floating Point MFC1 Move Word from Floating Point MFHC1 Move Word from High Half of Floating Point Register Release 2 Only MOV.fmt Floating Point Move MOVF.fmt Floating Point Move Conditional on Floating Point False MOVN.fmt Floating Point Move Conditional on Not Zero MOVT.fmt Floating Point Move Conditional on Floating Point True MOVZ.fmt Floating Point Move Conditional on Zero MTC1 Move Word to Floating Point MTHC1 Move Word to High Half of Floating Point Register Release 2 Only Table 3-17 Obsolete1 FPU Branch Instructions 1. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture. Mnemonic Instruction BC1FL Branch on FP False Likely BC1TL Branch on FP True Likely30 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 3.2 Alphabetical List of InstructionsTable 3-18 Coprocessor Branch Instructions Mnemonic Instruction BC2F Branch on COP2 False BC2T Branch on COP2 True Table 3-19 Coprocessor Execute Instructions Mnemonic Instruction COP2 Coprocessor Operation to Coprocessor 2 Table 3-20 Coprocessor Load and Store Instructions Mnemonic Instruction LDC2 Load Doubleword to Coprocessor 2 LWC2 Load Word to Coprocessor 2 SDC2 Store Doubleword from Coprocessor 2 SWC2 Store Word from Coprocessor 2 Table 3-21 Coprocessor Move Instructions Mnemonic Instruction CFC2 Move Control Word from Coprocessor 2 CTC2 Move Control Word to Coprocessor 2 MFC2 Move Word from Coprocessor 2 MFHC2 Move Word from High Half of Coprocessor 2 Register Release 2 Only MTC2 Move Word to Coprocessor 2 MTHC2 Move Word to High Half of Coprocessor 2 Register Release 2 Only Table 3-22 Obsolete1 Coprocessor Branch Instructions 1. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture. Mnemonic Instruction BC2FL Branch on COP2 False Likely BC2TL Branch on COP2 True Likely Table 3-23 Privileged Instructions Mnemonic Instruction CACHE Perform Cache OperationMIPS32™ Architecture For Programmers Volume II, Revision 2.00 31 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Chapter 3 The MIPS32™ Instruction SetDI Disable Interrupts Release 2 Only EI Enable Interrupts Release 2 Only ERET Exception Return MFC0 Move from Coprocessor 0 MTC0 Move to Coprocessor 0 RDPGPR Read GPR from Previous Shadow Set Release 2 Only TLBP Probe TLB for Matching Entry TLBR Read Indexed TLB Entry TLBWI Write Indexed TLB Entry TLBWR Write Random TLB Entry WAIT Enter Standby Mode WRPGPR Write GPR to Previous Shadow Set Release 2 Only Table 3-24 EJTAG Instructions Mnemonic Instruction DERET Debug Exception Return SDBBP Software Debug Breakpoint Table 3-23 Privileged Instructions Mnemonic Instruction32 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. MIPS32™ Architecture For Programmers Volume II, Revision 2.00 35 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. ADD.fmt Format: ADD.S fd, fs, ft MIPS32 ADD.D fd, fs, ft MIPS32 ADD.PS fd, fs, ft MIPS64 MIPS32 Release 2 Purpose: To add floating point values Description: fd ← fs + ft The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. ADD.PS adds the upper and lower halves of FPR fs and FPR ft independently, and ORs together any generated exceptions. Cause bits are ORed into the Flag bits if no exception is taken. Restrictions: The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE- DICTABLE. The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE. The result of ADD.PS is UNPREDICTABLE if the processor is executing in 16 FP registers mode. Operation: StoreFPR (fd, fmt, ValueFPR(fs, fmt) +fmt ValueFPR(ft, fmt)) Exceptions: Coprocessor Unusable, Reserved Instruction Floating Point Exceptions: Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow 31 26 25 21 20 16 15 11 10 6 5 0 COP1 010001 fmt ft fs fd ADD 000000 6 5 5 5 5 6 Floating Point Add ADD.fmt 36 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. ADDI Format: ADDI rt, rs, immediate MIPS32 Purpose: To add a constant to a 32-bit integer. If overflow occurs, then trap. Description: rt ← rs + immediate The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result. • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs. • If the addition does not overflow, the 32-bit result is placed into GPR rt. Restrictions: None Operation: temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 ≠ temp31 then SignalException(IntegerOverflow) else GPR[rt] ← temp endif Exceptions: Integer Overflow Programming Notes: ADDIU performs the same arithmetic operation but does not trap on overflow. 31 26 25 21 20 16 15 0 ADDI 001000 rs rt immediate 6 5 5 16 Add Immediate Word ADDI MIPS32™ Architecture For Programmers Volume II, Revision 2.00 37 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. ADDIU Format: ADDIU rt, rs, immediate MIPS32 Purpose: To add a constant to a 32-bit integer Description: rt ← rs + immediate The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rt. No Integer Overflow exception occurs under any circumstances. Restrictions: None Operation: temp ← GPR[rs] + sign_extend(immediate) GPR[rt]← temp Exceptions: None Programming Notes: The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith- metic environments that ignore overflow, such as C language arithmetic. 31 26 25 21 20 16 15 0 ADDIU 001001 rs rt immediate 6 5 5 16 Add Immediate Unsigned Word ADDIU Restrictions: The fields fs, ft, and fd must specify FPRs valid for operands of type PS. If they are not valid, the result is UNPRE- DICTABLE. If GPR rs1..0 are non-zero, the results are UNPREDICTABLE. The result of this instruction is UNPREDICTABLE if the processor is executing in 16 FP registers mode. Operation: if GPR[rs]2..0 = 0 then StoreFPR(fd, PS,ValueFPR(fs,PS)) else if GPR[rs]2..0 ≠ 4 then UNPREDICTABLE else if BigEndianCPU then StoreFPR(fd, PS, ValueFPR(fs, PS)31..0 || ValueFPR(ft,PS)63..32) else StoreFPR(fd, PS, ValueFPR(ft, PS)31..0 || ValueFPR(fs,PS)63..32) endif Exceptions: Coprocessor Unusable, Reserved Instruction Programming Notes: ALNV.PS is designed to be used with LUXC1 to load 8 bytes of data from any 4-byte boundary. For example: /* Copy T2 bytes (a multiple of 16) of data T0 to T1, T0 unaligned, T1 aligned. Reads one dw beyond the end of T0. */ LUXC1 F0, 0(T0) /* set up by reading 1st src dw */ LI T3, 0 /* index into src and dst arrays */ ADDIU T4, T0, 8 /* base for odd dw loads */ ADDIU T5, T1, -8/* base for odd dw stores */ LOOP: LUXC1 F1, T3(T4) ALNV.PS F2, F0, F1, T0/* switch F0, F1 for little-endian */ SDC1 F2, T3(T1) ADDIU T3, T3, 16 LUXC1 F0, T3(T0) ALNV.PS F2, F1, F0, T0/* switch F1, F0 for little-endian */ BNE T3, T2, LOOP SDC1 F2, T3(T5) DONE: Floating Point Align Variable (cont.) ALNV.PS40 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. ALNV.PS is also useful with SUXC1 to store paired-single results in a vector loop to a possibly misaligned address: /* T1[i] = T0[i] + F8, T0 aligned, T1 unaligned. */ CVT.PS.S F8, F8, F8/* make addend paired-single */ /* Loop header computes 1st pair into F0, stores high half if T1 */ /* misaligned */ LOOP: LDC1 F2, T3(T4)/* get T0[i+2]/T0[i+3] */ ADD.PS F1, F2, F8/* compute T1[i+2]/T1[i+3] */ ALNV.PS F3, F0, F1, T1/* align to dst memory */ SUXC1 F3, T3(T1)/* store to T1[i+0]/T1[i+1] */ ADDIU T3, 16 /* i = i + 4 */ LDC1 F2, T3(T0)/* get T0[i+0]/T0[i+1] */ ADD.PS F0, F2, F8/* compute T1[i+0]/T1[i+1] */ ALNV.PS F3, F1, F0, T1/* align to dst memory */ BNE T3, T2, LOOP SUXC1 F3, T3(T5)/* store to T1[i+2]/T1[i+3] */ /* Loop trailer stores all or half of F0, depending on T1 alignment */ Floating Point Align Variable (cont.) ALNV.PSMIPS32™ Architecture For Programmers Volume II, Revision 2.00 41 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 42 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. AND Format: AND rd, rs, rt MIPS32 Purpose: To do a bitwise logical AND Description: rd ← rs AND rt The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd. Restrictions: None Operation: GPR[rd] ← GPR[rs] and GPR[rt] Exceptions: None 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 AND 100100 6 5 5 5 5 6 And AND MIPS32™ Architecture For Programmers Volume II, Revision 2.00 45 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BAL Format: BAL rs, offset Assembly Idiom Purpose: To do an unconditional PC-relative procedure call Description: procedure_call BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the hardware as BGEZAL r0, offset. Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call. An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot. Operation: I: target_offset ← sign_extend(offset || 02) GPR[31] ← PC + 8 I+1: PC ← PC + target_offset Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range. 31 26 25 21 20 16 15 0 REGIMM 000001 0 00000 BGEZAL 10001 offset 6 5 5 16 Branch and Link BAL BC1F Format: BC1F offset (cc = 0 implied) MIPS32 BC1F cc, offset MIPS32 Purpose: To test an FP condition code and do a PC-relative conditional branch Description: if cc = 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd. I: condition ← FPConditionCode(cc) = 0 target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC ← PC + target_offset endif 31 26 25 21 20 18 17 16 15 0 COP1 010001 BC 01000 cc nd 0 tf 0 offset 6 5 3 1 1 16 Branch on FP False BC1F46 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Exceptions: Coprocessor Unusable, Reserved Instruction Floating Point Exceptions: Unimplemented Operation Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range Historical Information: The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section. The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32. In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction. Branch on FP False (cont.) BC1FMIPS32™ Architecture For Programmers Volume II, Revision 2.00 47 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BC1T Format: BC1T offset (cc = 0 implied) MIPS32 BC1T cc, offset MIPS32 Purpose: To test an FP condition code and do a PC-relative conditional branch Description: if cc = 1 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd. I: condition ← FPConditionCode(cc) = 1 target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC ← PC + target_offset endif 31 26 25 21 20 18 17 16 15 0 COP1 010001 BC 01000 cc nd 0 tf 1 offset 6 5 3 1 1 16 Branch on FP True BC1T50 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Exceptions: Coprocessor Unusable, Reserved Instruction Floating Point Exceptions: Unimplemented Operation Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Historical Information: The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section. The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32. In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction. Branch on FP True (cont.) BC1TMIPS32™ Architecture For Programmers Volume II, Revision 2.00 51 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BC1TL Format: BC1TL offset (cc = 0 implied) MIPS32 BC1TL cc, offset MIPS32 Purpose: To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken. Description: if cc = 1 then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con- dition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. An FP condition code is set by the FP compare instruction, C.cond.fmt. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd. I: condition ← FPConditionCode(cc) = 1 target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif 31 26 25 21 20 18 17 16 15 0 COP1 010001 BC 01000 cc nd 1 tf 1 offset 6 5 3 1 1 16 Branch on FP True Likely BC1TL52 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BC2FL Format: BC2FL offset (cc = 0 implied) MIPS32 BC2FL cc, offset MIPS32 Purpose: To test a COP2 condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken. Description: if cc = 0 then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd. I: condition ← COP2Condition(cc) = 0 target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif 31 26 25 21 20 18 17 16 15 0 COP2 010010 BC 01000 cc nd 1 tf 0 offset 6 5 3 1 1 16 Branch on COP2 False Likely BC2FLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 55 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Exceptions: Coprocessor Unusable, Reserved Instruction Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC2F instruction instead. Branch on COP2 False Likely (cont.) BC2FL56 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. MIPS32™ Architecture For Programmers Volume II, Revision 2.00 57 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BC2T Format: BC2T offset (cc = 0 implied) MIPS32 BC2T cc, offset MIPS32 Purpose: To test a COP2 condition code and do a PC-relative conditional branch Description: if cc = 1 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd. I: condition ← COP2Condition(cc) = 1 target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC ← PC + target_offset endif Exceptions: Coprocessor Unusable, Reserved Instruction Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. 31 26 25 21 20 18 17 16 15 0 COP2 010010 BC 01000 cc nd 0 tf 1 offset 6 5 3 1 1 16 Branch on COP2 True BC2T 60 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BEQ Format: BEQ rs, rt, offset MIPS32 Purpose: To compare GPRs then do a PC-relative conditional branch Description: if rs = rt then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] = GPR[rt]) I+1: if condition then PC ← PC + target_offset endif Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. BEQ r0, r0 offset, expressed as B offset, is the assembly idiom used to denote an unconditional branch. 31 26 25 21 20 16 15 0 BEQ 000100 rs rt offset 6 5 5 16 Branch on Equal BEQ BEQL Format: BEQL rs, rt, offset MIPS32 Purpose: To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if rs = rt then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are equal, branch to the target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] = GPR[rt]) I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 BEQL 010100 rs rt offset 6 5 5 16 Branch on Equal Likely BEQLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 61 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BEQ instruction instead. Historical Information: In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception. Branch on Equal Likely (cont.) BEQL62 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BGEZALL Format: BGEZALL rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken. Description: if rs ≥ 0 then procedure_call_likely Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call. An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot. Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN GPR[31] ← PC + 8 I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 REGIMM 000001 rs BGEZALL 10011 offset 6 5 5 16 Branch on Greater Than or Equal to Zero and Link Likely BGEZALLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 65 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range. Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGEZAL instruction instead. Historical Information: In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception. Branch on Greater Than or Equal to Zero and Link Likely (con’t.) BGEZALL66 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BGEZL Format: BGEZL rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if rs ≥ 0 then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 REGIMM 000001 rs BGEZL 00011 offset 6 5 5 16 Branch on Greater Than or Equal to Zero Likely BGEZLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 67 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BGTZL Format: BGTZL rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if rs > 0 then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not exe- cuted. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] > 0GPRLEN I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 BGTZL 010111 rs 0 00000 offset 6 5 5 16 Branch on Greater Than Zero Likely BGTZL70 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGTZ instruction instead. Historical Information: In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception. Branch on Greater Than Zero Likely (cont.) BGTZLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 71 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. 72 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BLEZ Format: BLEZ rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional branch Description: if rs ≤ 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≤ 0GPRLEN I+1: if condition then PC ← PC + target_offset endif Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 BLEZ 000110 rs 0 00000 offset 6 5 5 16 Branch on Less Than or Equal to Zero BLEZ MIPS32™ Architecture For Programmers Volume II, Revision 2.00 75 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BLTZ Format: BLTZ rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional branch Description: if rs < 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN I+1: if condition then PC ← PC + target_offset endif Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range. 31 26 25 21 20 16 15 0 REGIMM 000001 rs BLTZ 00000 offset 6 5 5 16 Branch on Less Than Zero BLTZ 76 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BLTZAL Format: BLTZAL rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional procedure call Description: if rs < 0 then procedure_call Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call. An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. Restrictions: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot. Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN GPR[31] ← PC + 8 I+1: if condition then PC ← PC + target_offset endif Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range. 31 26 25 21 20 16 15 0 REGIMM 000001 rs BLTZAL 10000 offset 6 5 5 16 Branch on Less Than Zero and Link BLTZAL BLTZALL Format: BLTZALL rs, offset MIPS32 Purpose: To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken. Description: if rs < 0 then procedure_call_likely Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call. An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot. Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN GPR[31] ← PC + 8 I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 REGIMM 000001 rs BLTZALL 10010 offset 6 5 5 16 Branch on Less Than Zero and Link Likely BLTZALLMIPS32™ Architecture For Programmers Volume II, Revision 2.00 77 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLTZ instruction instead. Historical Information: In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception. Branch on Less Than Zero Likely (cont.) BLTZL80 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. MIPS32™ Architecture For Programmers Volume II, Revision 2.00 81 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. BNE Format: BNE rs, rt, offset MIPS32 Purpose: To compare GPRs then do a PC-relative conditional branch Description: if rs ≠ rt then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] ≠ GPR[rt]) I+1: if condition then PC ← PC + target_offset endif Exceptions: None Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 BNE 000101 rs rt offset 6 5 5 16 Branch on Not Equal BNE BNEL Format: BNEL rs, rt, offset MIPS32 Purpose: To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if rs ≠ rt then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed. Restrictions: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Operation: I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] ≠ GPR[rt]) I+1: if condition then PC ← PC + target_offset else NullifyCurrentInstruction() endif Exceptions: None 31 26 25 21 20 16 15 0 BNEL 010101 rs rt offset 6 5 5 16 Branch on Not Equal Likely BNEL82 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. C.cond.fmt Format: C.cond.S fs, ft (cc = 0 implied) MIPS32 C.cond.D fs, ft (cc = 0 implied) MIPS32 C.cond.PS fs, ft(cc = 0 implied) MIPS64 MIPS32 Release 2 C.cond.S cc, fs, ft MIPS32 C.cond.D cc, fs, ft MIPS32 C.cond.PS cc, fs, ft MIPS64 MIPS32 Release 2 Purpose: To compare FP values and record the Boolean result in a condition code Description: cc ← fs compare_cond ft The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The comparison is exact and nei- ther overflows nor underflows. If the comparison specified by cond2..1 is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into condition code CC; true is 1 and false is 0. c.cond.PS compares the upper and lower halves of FPR fs and FPR ft independently and writes the results into condi- tion codes CC +1 and CC respectively. The CC number must be even. If the number is not even the operation of the instruction is UNPREDICTABLE. If one of the values is an SNaN, or cond3 is set and at least one of the values is a QNaN, an Invalid Operation condi- tion is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise, the Boolean result is written into condition code CC. There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0. The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal, equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Bool- ean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP val- ues in the equation. If the equal relation is true, for example, then all four example predicates above yield a true result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result. Logical negation of a compare result allows eight distinct comparisons to test for the 16 predicates as shown in . Each mnemonic tests for both a predicate and its logical negation. For each mnemonic, compare tests the truth of the first predicate. When the first predicate is true, the result is true as shown in the “If Predicate Is True” column, and the sec- ond predicate must be false, and vice versa. (Note that the False predicate is never true and False/True do not follow the normal pattern.) The truth of the second predicate is the logical negation of the instruction result. After a compare instruction, test for the truth of the first predicate can be made with the Branch on FP True (BC1T) instruction and the truth of the second can be made with Branch on FP False (BC1F). 31 26 25 21 20 16 15 11 10 8 7 6 5 4 3 0 COP1 010001 fmt ft fs cc 0 A 0 FC 11 cond 6 5 5 5 3 1 1 2 4 Floating Point Compare C.cond.fmtMIPS32™ Architecture For Programmers Volume II, Revision 2.00 85 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Table 3-25 shows another set of eight compare operations, distinguished by a cond3 value of 1 and testing the same 16 conditions. For these additional comparisons, if at least one of the operands is a NaN, including Quiet NaN, then an Invalid Operation condition is raised. If the Invalid Operation condition is enabled in the FCSR, an Invalid Operation exception occurs. Table 3-25 FPU Comparisons Without Special Operand Exceptions Instruction Comparison Predicate Comparison CC Result Instruction Cond Mnemonic Name of Predicate and Logically Negated Predicate (Abbreviation) Relation Values If Predicate Is True Inv Op Excp. if QNaN ? Condition Field > < = ? 3 2..0 F False [this predicate is always False] F F F F F No 0 0 True (T) T T T T UN Unordered F F F T T 1 Ordered (OR) T T T F F EQ Equal F F T F T 2 Not Equal (NEQ) T T F T F UEQ Unordered or Equal F F T T T 3 Ordered or Greater Than or Less Than (OGL) T T F F F OLT Ordered or Less Than F T F F T 4 Unordered or Greater Than or Equal (UGE) T F T T F ULT Unordered or Less Than F T F T T 5 Ordered or Greater Than or Equal (OGE) T F T F F OLE Ordered or Less Than or Equal F T T F T 6 Unordered or Greater Than (UGT) T F F T F ULE Unordered or Less Than or Equal F T T T T 7 Ordered or Greater Than (OGT) T F F F F Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False Floating Point Compare (cont.) C.cond.fmt86 MIPS32™ Architecture For Programmers Volume II, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved. Table 3-26 FPU Comparisons With Special Operand Exceptions for QNaNs Instruction Comparison Predicate Comparison CC Result Instructio n Cond Mnemonic Name of Predicate and Logically Negated Predicate (Abbreviation) Relation Values If Predicate Is True Inv Op Excp If QNaN? Condition Field > < = ? 3 2..0 SF Signaling False [this predicate always False] F F F F F Yes 1 0 Signaling True (ST) T T T T NGLE Not Greater Than or Less Than or Equal F F F T T 1 Greater Than or Less Than or Equal (GLE) T T T F F SEQ Signaling Equal F F T F T 2 Signaling Not Equal (SNE) T T F T F NGL Not Greater Than or Less Than F F T T T 3 Greater Than or Less Than (GL) T T F F F LT Less Than F T F F T 4 Not Less Than (NLT) T F T T F NGE Not Greater Than or Equal F T F T T 5 Greater Than or Equal (GE) T F T F F LE Less Than or Equal F T T F T 6 Not Less Than or Equal (NLE) T F F T F NGT Not Greater Than F T T T T 7 Greater Than (GT) T F F F F Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False Floating Point Compare (cont.) C.cond.fmtMIPS32™ Architecture For Programmers Volume II, Revision 2.00 87 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.