Arithmetic for Computers: Arithmetic Operations on Integers and Floating-Point Numbers, Exams of Computer Architecture and Organization

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Chapter 3 Arithmetic for Computers Chapter 3 — Arithmetic for Computers — 2 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation and operations §3.1 Introduction Overflow conditions Overflow conditions for addition and subtraction Chapter 3 — Arithmetic for Computers — 5 Chapter 3 — Arithmetic for Computers — 6 Dealing with Overflow Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action Chapter 3 — Arithmetic for Computers — 7 Arithmetic for Multimedia Graphics and media processing operates on vectors of 8-bit and 16-bit data Use 64-bit adder, with partitioned carry chain Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors SIMD (single-instruction, multiple-data) Saturating operations On overflow, result is largest representable value c.f. 2s-complement modulo arithmetic E.g., clipping in audio, saturation in video Chapter 3 — Arithmetic for Computers — 10 Multiplication Start with long-multiplication approach 1000 × 1001 1000 0000 0000 1000 1001000 Length of product = length of multiplicand + length + multiplier, if we ignore the sign bits multiplicand multiplier product §3.3 M ultiplication Multiplication hardware is simply shifts and adds Chapter 3 — Arithmetic for Computers — 11 Multiplication Hardware Initially 0 1000 × 1001 1000 0000 0000 1000 1001000 Takes about 100 cycles if each step takes 1 cycle Chapter 3 — Arithmetic for Computers — 12 Optimized Multiplier Perform steps in parallel: add/shift Multiplier and multiplicand are shifted while the multiplicand is added to the product One cycle per partial-product addition That’s ok, if frequency of multiplications is low 1000 × 1001 1000 0000 0000 1000 1001000 Chapter 3 — Arithmetic for Computers — 15 Division Check for 0 divisor Long division approach If divisor ≤ dividend bits 1 bit in quotient, subtract Otherwise 0 bit in quotient, bring down next dividend bit Restoring division Do the subtract, and if remainder goes < 0, add divisor back Signed division Divide using absolute values Adjust sign of quotient and remainder as required Dividend = Quotient x Divisor + Remainder quotient dividend remainder 1001 1000 1001010 -1000 10 101 1010 -1000 10 divisor §3.4 D ivision Chapter 3 — Arithmetic for Computers — 16 Division Hardware Initially dividend Initially divisor in left half 1001 1000 1001010 -1000 10 101 1010 -1000 10 Chapter 3 — Arithmetic for Computers — 17 Optimized Divider One cycle per partial-remainder subtraction Remainder is shifted left Reminder in the HI, quotient on the LO Looks a lot like a multiplier! Same hardware can be used for both Chapter 3 — Arithmetic for Computers — 20 Floating Point Representation for non-integral numbers Including very small and very large numbers Like scientific notation –2.34 × 1056 +0.002 × 10–4 +987.02 × 109 In binary ±1.xxxxxxx2 × 2yyyy Types float and double in C normalized not normalized §3.5 Floating P oint Chapter 3 — Arithmetic for Computers — 21 Floating Point Standard Defined by IEEE Std 754-1985 Primary architect: William Kahan (1989 Turing award winner) Developed in response to divergence of representations Portability issues for scientific code Now almost universally adopted Two representations Single precision (32-bit) Double precision (64-bit) Chapter 3 — Arithmetic for Computers — 22 IEEE Floating-Point Format S: sign bit (0 ⇒ non-negative, 1 ⇒ negative) Normalize significand: 1.0 ≤ |significand| < 2.0 Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the “1.” restored Exponent: excess representation: actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = 1203 S Exponent Fraction single: 8 bits double: 11 bits single: 23 bits double: 52 bits Bias)(ExponentS 2Fraction)(11)(x −×+×−= Chapter 3 — Arithmetic for Computers — 25 Floating-Point Precision Relative precision all fraction bits are significant Single: approx 2–23 Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal digits of precision Double: approx 2–52 Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal digits of precision Chapter 3 — Arithmetic for Computers — 26 Floating-Point Example Represent –0.75 –0.75 = (–1)1 × 1.12 × 2–1 S = 1 Fraction = 1000…002 Exponent = –1 + Bias Single: –1 + 127 = 126 = 011111102 Double: –1 + 1023 = 1022 = 011111111102 Single: 1011111101000…00 Double: 1011111111101000…00 Chapter 3 — Arithmetic for Computers — 27 Floating-Point Example What number is represented by the single- precision float 11000000101000…00 S = 1 Fraction = 01000…002 Fxponent = 100000012 = 129 x = (–1)1 × (1 + 012) × 2(129 – 127) = (–1) × 1.25 × 22 = –5.0 Chapter 3 — Arithmetic for Computers — 32 FP Adder Hardware Much more complex than integer adder Doing it in one clock cycle would take too long Much longer than integer operations Slower clock would penalize all instructions FP adder usually takes several cycles Can be pipelined Chapter 3 — Arithmetic for Computers — 33 FP Adder Hardware Step 1 Step 2 Step 3 Step 4 Chapter 3 — Arithmetic for Computers — 36 FP Arithmetic Hardware FP multiplier is of similar complexity to FP adder But uses a multiplier for significands instead of an adder FP arithmetic hardware usually does Addition, subtraction, multiplication, division, reciprocal, square-root FP ↔ integer conversion Operations usually takes several cycles Can be pipelined Chapter 3 — Arithmetic for Computers — 39 FP Example: °F to °C C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr - 32.0)); } fahr in $f12, result in $f0, literals in global memory space Compiled MIPS code: f2c: lwc1 $f16, const5($gp) lwc2 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra Chapter 3 — Arithmetic for Computers — 40 FP Example: Array Multiplication X = X + Y × Z All 32 × 32 matrices, 64-bit double-precision elements C code: void mm (double x[][], double y[][], double z[][]) { int i, j, k; for (i = 0; i! = 32; i = i + 1) for (j = 0; j! = 32; j = j + 1) for (k = 0; k! = 32; k = k + 1) x[i][j] = x[i][j] + y[i][k] * z[k][j]; } Addresses of x, y, z in $a0, $a1, $a2, and i, j, k in $s0, $s1, $s2 Chapter 3 — Arithmetic for Computers — 41 FP Example: Array Multiplication MIPS code: li $t1, 32 # $t1 = 32 (row size/loop end) li $s0, 0 # i = 0; initialize 1st for loop L1: li $s1, 0 # j = 0; restart 2nd for loop L2: li $s2, 0 # k = 0; restart 3rd for loop sll $t2, $s0, 5 # $t2 = i * 32 (size of row of x) addu $t2, $t2, $s1 # $t2 = i * size(row) + j sll $t2, $t2, 3 # $t2 = byte offset of [i][j] addu $t2, $a0, $t2 # $t2 = byte address of x[i][j] l.d $f4, 0($t2) # $f4 = 8 bytes of x[i][j] L3: sll $t0, $s2, 5 # $t0 = k * 32 (size of row of z) addu $t0, $t0, $s1 # $t0 = k * size(row) + j sll $t0, $t0, 3 # $t0 = byte offset of [k][j] addu $t0, $a2, $t0 # $t0 = byte address of z[k][j] l.d $f16, 0($t0) # $f16 = 8 bytes of z[k][j] … Chapter 3 — Arithmetic for Computers — 45 Associativity Parallel programs may interleave operations in unexpected orders Assumptions of associativity may fail §3.6 P arallelism and C om puter A rithm etic: A ssociativity (x+y)+z x+(y+z) x -1.50E+38 -1.50E+38 y 1.50E+38 z 1.0 1.0 1.00E+00 0.00E+00 0.00E+00 1.50E+38 Need to validate parallel programs under varying degrees of parallelism Chapter 3 — Arithmetic for Computers — 46 x86 FP Architecture Originally based on 8087 FP coprocessor 8 × 80-bit extended-precision registers Used as a push-down stack Registers indexed from TOS: ST(0), ST(1), … FP values are 32-bit or 64 in memory Converted on load/store of memory operand Integer operands can also be converted on load/store Very difficult to generate and optimize code Result: poor FP performance §3.7 R eal S tuff: Floating P oint in the x86 Chapter 3 — Arithmetic for Computers — 47 x86 FP Instructions Optional variations I: integer operand P: pop operand from stack R: reverse operand order But not all combinations allowed Data transfer Arithmetic Compare Transcendental FILD mem/ST(i) FISTP mem/ST(i) FLDPI FLD1 FLDZ FIADDP mem/ST(i) FISUBRP mem/ST(i) FIMULP mem/ST(i) FIDIVRP mem/ST(i) FSQRT FABS FRNDINT FICOMP FIUCOMP FSTSW AX/mem FPATAN F2XMI FCOS FPTAN FPREM FPSIN FYL2X Chapter 3 — Arithmetic for Computers — 50 Who Cares About FP Accuracy? Important for scientific code But for everyday consumer use? “My bank balance is out by 0.0002¢!” The Intel Pentium FDIV bug The market expects accuracy See Colwell, The Pentium Chronicles Chapter 3 — Arithmetic for Computers — 51 Concluding Remarks ISAs support arithmetic Signed and unsigned integers Floating-point approximation to reals Bounded range and precision Operations can overflow and underflow MIPS ISA Core instructions: 54 most frequently used 100% of SPECINT, 97% of SPECFP Other instructions: less frequent §3.9 C oncluding R em arks