Download Array Multiplier - Advanced VLSI Design and Applications | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nArray Multiplier Could take 3 bits at time (radix 8), but need 3x, 5x, 6x, 7x multiplicand. a a a a a a b b b b b b p1p1p1p1p1p1 p2p2p2p2p2p2 longest delay pnpnpnpnpnpn delay ~ # digits in word + # partial products # partial products can be reduced by using radix > 2 multiplier multiplicand multiplier1 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 must pre-calculate 3 x multiplicand 1 0 1 1 1 0 3 1 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0Array Multiplier October 20, 2000 page 1 of 10 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nTrick: recode multiplier changing all 3’s to 4 - 1. This can be done with a shifter and 2’s complement hardware and does not need an extra adder. Example Booth algorithm replaces any string of 1’s (including 3’s) with single digits isolated by strings of 0’s. Booth recoding Example Now that 3’s are gone, combine each pair bits into single recorded digit to reduce number of partial products. 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 (+1)(+1)(-1) 1 0 3 1 1 -1 sign extension of negative partial product 01111110 ⇔ 10000000 00000010– 10000010 bi bi 1– bi 0 0 0 0 1 1 1 0 1 1 1 0 (recoded) left side of string of 1’s right side of string of 1’s (original) multiplier 0 1 0 0 1 1 assume zero recoded multiplier 1 1 0 1 0 1 (+1) (+1) (-1)Array Multiplier October 20, 2000 page 2 of 10 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nCarry Save Adder (CSA) Partial Product Generator recoded digit operation 0 0 => partial product + 1 multiplicand => partial product + 2 shifted multiplicand => partial product - 1 complemented multiplicand => partial product - 2 shifted & complemented multiplicand => partial product FA FA FA FA FA FA No carry delay! (within a CSA stage) CSA array Fast Adder CSA CSA CS CS CS CSArray Multiplier October 20, 2000 page 5 of 10 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nCarry Generation ZERO Ai Ai-1 COMP MUX MUXSHIFT P.P.i P.P.i-1 ZERO COMP SHIFT Cin . two ways to get a “zero” p.p.p.p. bits Cin 000 0 0 111 1 1Array Multiplier October 20, 2000 page 6 of 10 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nMultiplier Encoder Sign Extension Problem original example bi+1 bi bi-1 Recoded Digit COMP SHIFT ZERO 0 0 0 0 x x 1 0 0 1 +1 0 0 0 0 1 0 +1 0 0 0 0 1 1 +2 0 1 0 1 0 0 -2 1 1 0 1 0 1 -1 1 0 0 1 1 0 -1 1 0 0 1 1 1 0 x x 1 COMP bi 1+= SHIFT bi bi 1– bi bi 1–⋅+⋅= ZERO bi 1+ bi bi 1– bi 1+ bi bi 1–⋅ ⋅+⋅ ⋅= 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 sign extension regard as negative numberArray Multiplier October 20, 2000 page 7 of 10
