Assignment 1 for Advanced VLSI Architecture Design | ENEE 640, Assignments of Electrical and Electronics Engineering

Download Assignment 1 for Advanced VLSI Architecture Design | ENEE 640 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! SOLUTIONS TO ASSIGNMENT NO.1 3. The given nonrecursive signal processing structure is shown as D DD DDD D D X1(n) X2(n) a1 a2 a3 b1 b3b2 a4 a5 b4 b5 Y(n)0 There are two critical paths, one from X1(n) to Y(n) and the other from X2(n) to Y(n). The iteration along such a path is given by Tsample = Tm +5 Ta We can reduce this time period by dividing the whole circuit into two parts as below and using transposition on each part. Transposing part 1 yields D DDD X1(n) a5 a4 a3 a2 a1 Y(n)0 Thus equivalent broadcast structure is given by X2(n) Y(n)0 b5 b3b4 b2 b1 D DDD X1(n) a5 a4 a3 a2 a1 The iteration period for this broadcast circuit is Tsample =Tm + Ta Number of samples processed per second (throughput) is given by 1/ (Tm + Ta). 7. (a) The 6th-order FIR filter is given by y(n)= ax(n) + bx(n-4) +cx(n-6) This circuit is represented in block diagram by 4D 2D x(n) a b c y(n) There are two critical paths from x(n) to y(n) .The iteration along critical path is given by Tsample = Tm +2 Ta To limit the clock period by one multiply-add time we use transposition on the circuit above and get the new circuit as x(n) c b a y(n)4D 2D The new time period of each output sample for the new transposed circuit is given by Tsample = Tm + Ta 7(b) . Block architecture for the circuit 6th-order FIR filter of block size of 3 using parallel processing is given by equations y(3k) = ax(3k) +bx(3k-4)+cx(3k-6) y(3k+1) = ax(3k+1) +bx(3k-3)+cx(3k-5) y(3k+2) = ax(3k+2) +bx(3k-2)+cx(3k-4) 8(a). The given recursive filter is x(n) = ax(n-2) + u(n) The circuit above is given by x(n)u(n) 2D a Breaking up the multiply-add operation into 2 components is done by using two Multiply Add Components (MAC) which is given by the figure MAC a Z u(n) Output = u(n) + aZ In our circuit MAC is represented by MAC a u(n) x(n) 2D x(n) = ax(n-2) + u(n) x(n-2) Redistributing the delay elements in the loop is given by MAC1 u(n) D x(n-1) MAC2 D 0 u(n) x(n) 8(b). The given equation is y(n) = by(n-2) + v(n) First slow down the circuit by replacing the 2-delay with a 4-delay and then interleave the two computations. There appears an idle cycle in every two cycles. These idle cycles are used to operate v(n). MAC a,b ……..v2(n),u2(n),v1(n),u1(n) x1(n),y1(n),x2(n),y2(n),x3(n)………... 4D Time 1 2 3 4 5 6 7 8 9 ……. Input u1 v1 u2 v2 u3 v3 u4 v4 v5 ...… Output x1 y1 x2 y2 x3 y3 x4 y4 x5 …….. Pipelining the multiply-add operation by 4 stages we get MAC1 D u(n) x(n) MAC2 D 0 MAC3 D 0 MAC4 0 D 9. Given that Threshold voltage Vt = 0.4 V Initial Voltage supply Vo = 5 V Let the level of pipelining be M Let β is the voltage reduction factor i.e. supply voltage can be reduced to βVo for the pipelined system. From (1) and (1a) we get β2 <=1/5 => β =√5 =0.447 Suppose that the pipelined system and the original system have the same sample rate, we have M= β (Vo - Vt )2 (βVo - Vt )2 Using the values of Vo, Vt & β and solving for M we get M= ┌ 0.447(5- 0.4) 2 ┐ (0.447 * 5 -0.4) 2 =┌ 2.8 ┐ = 3 Therefore, the system should be pipelined at 3 level. Substitute M=3 into (3.9) and solve for β =0.427. The supply voltage for pipelined system is βVo = 0.427* 5 V = 2.14 Volts. 10. Given that As required, filter (a) and filter (b) have equal clock period, therefore: Ccharge(a)Va = Ccharge(b)Vb k(Va - Vt )2 k(Vb - Vt )2 From the filter structure we know Tcritical =9Ta for filter (a), Tcritical =4Ta For filter(b), Ccharge(a) = Propagation delay of circuit A(Tcritical(a)) = Vb * (Va-Vt)2 Ccharge(b) Propagation delay of circuit B (Tcritical(b)) Va * (Vb-Vt)2 Substitute the values of Va = 4 V and Vt = 0.5 V, we have: 36(Vb)2 - 85Vb + 9 = 0 Vb1 =2.25 Volt Vb2 =0.11 Volt-------discarded Compare to filter(a) ,the ratio of power saved by filter (b) is 1- (Vb)2 = 1- 2.252 = 68.34% (Va) 42