Download Assignment 5 for Advanced VLSI Architecture Design | ENEE 640 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! Solutions to Assignment #5 Chapter 7 1 (a) From the DFG we get: ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ = 0 1 , 1 1 , 1 0 hyx eee The two conditions to be satisfied for the scheduling and the projection vector to be permissible are: ,0 ,0 ≥ ≠ eS dS T T for all dependence vectors e. Verifying these conditions we get the following for each of the cases: (i) [ ] [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⇒== 1 0 0101 pdS TT epT eS T xe 1 0 ye 1 1 he 0 1 In this case 0 1 ≥ = eSAll dS T T Thus this case is permissible. (ii) [ ] [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⇒−== 2 1 1221 pdS TT [ ] 0 1 2 21 =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − =dSSince T , this case is not permissible. (iii) [ ] [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⇒== 1 0 0111 pdS TT epT eS T xe 1 1 ye 1 2 he 0 1 In this case 0 1 ≥ = eSAll dS T T Thus this case is permissible. (iv) [ ] [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⇒=−= 1 0 0121 pdS TT In this case [ ] 1 0 1 21 =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ −=dS T , [ ] 02 1 0 21 <−=⎥ ⎦ ⎤ ⎢ ⎣ ⎡ −= iseS x T [ ] 01 1 1 21 <−=⎥ ⎦ ⎤ ⎢ ⎣ ⎡ −= iseS y T , [ ] 1 0 1 21 =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ −=h T eS Since 0<eS T for e= ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ 1 0 and e= ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ 1 1 this case is not permissible. Note that these edges cannot be simply reversed to make 0≥eST since the functionality of the nodes in the dependence graph are unknown and it is not clear if there are precedence constraints along the edges. (b) The systolic architectures for the permissible designs (i) and (iii) are given below. P0 P1 P2 .........X3X2X1X0 .........Y3Y2Y1Y0 D D D D D h0 h1 h2 D Figure1. [ ] [ ]TT dS 0101 == P0 P1 P2 .........X3X2X1X0 .........Y3Y2Y1Y0 D 2D D D 2D h0 h1 h2 D D 2D D Figure2. [ ] [ ]TT dS 0111 == epT eS T xe 1 0 ye 0 4 he 1 4 The systolic architecture for the design is given below. P0 P1 P2 4D 4D 4D Y Y 4D 4D P3 4D Y 4D P4 4D Y 4D Y w4 w3 w2 w1 w0 X Figure 4. [ ] [ ]TT dS 1104 −== 10. i j The dependence vectors are given by: ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ = 1 0 , 0 2 , 0 1 hyx eee (a) Since there is a delay on each edge, we can choose [ ]TS 11= [ ] [ ] ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⇒== 0 1 1011 pdS TT HUE= 1/STd =1 epT eS T xe 1 1 ye 2 2 he 0 1 The systolic architecture for the design is given below. Figure 5. [ ] [ ]TT dS 1011 == (b) If ( ) ⎥ ⎦ ⎤ ⎢ ⎣ ⎡− =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − =⇒=⎥ ⎦ ⎤ ⎢ ⎣ ⎡ = 1 1 1 1 11, 1 1 porpSd T choosing p= ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ −1 1 epT eS T xe 1 1 ye 2 2 he -1 1 The systolic architecture for the design is given below. 2D 2D 2D2D 2D X Y D D D D D 2D h D D D D D D D Figure 6. [ ] [ ]TT dS 1111 == 2D 2D 2D2D 2D X Y D D D D D h h h h h D D D D 15. Y(n) is defined by the following equation: )6()4()2()()( −+−+−+= ndxncxnbxnaxny In the given DG the inputs move along the “j” axis, the weights along the “i” axis, and the outputs move along the diagonal. Note that the dependence vectors are given by: ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ = 0 1 , 1 2 , 1 0 hyx eee (a) For such a filter the RIA is given by )1,(),( ),(),()1,2(),( ),1(),( −= ++−= −= jiXjiX jiHjiXjiYjiY jiHjiH The reduced graph is given as H (1 0) Y (2, -1) X (0,0) (0,0) (0, 1) x0 x1 x2 x3 x4 x5 y6 a b c d x6 x7 y7 y8 i j
