Assignment No 04 - Lecture notes 1, Assignments of Electronics

Download Assignment No 04 - Lecture notes 1 and more Assignments Electronics in PDF only on Docsity! 12 Lab 12 - Implementation of Synchronous Counter using Flip Flops 12.1 Objective To understand the working of a synchronous counter using the flip flops basic knowledge. 12.2 Theory 12.2.1Synchronous Counter The external clock signal is connected to the clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. In other words, changes in the output occur in “synchronization” with the clock signal. The result of this synchronization is that all the individual output bits changing state at exactly the same time in response to the common clock signal with no ripple effect and therefore, no propagation delay. 12.2.2Triggering A Synchronous Counter Synchronous Counters use edge-triggered flip-flops that change states on either the “positive-edge” (rising edge) or the “negative-edge” (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal. It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next. This works because the next bit must change state when the previous bit changes from high to low – the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays. Figure 12-1 : Binary 4-bit Synchronous Up Counter It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse. The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied with signals from the input and output of the previous stage. These additional AND gates generate the required logic for the JK inputs of the next stage. If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. Then as there is no inherent propagation delay in synchronous counters, because all the counter stages are triggered in parallel at the same time, the maximum operating frequency of this type of frequency counter is much higher than that for a similar asynchronous counter circuit. 6. Now remove the clock source and connect this input to the switch of your trainer board S0. 7. Turn on and off the switch, and note down your observations again in the results section. 12.6 Results 12.6.1Experiment A: Design of Synchronous Up Counter Note down your observation in the space provided below for both the cases: i- When CLK input is provided from function generator ii- When CLK input is provided from a switch S0. 12.6.2Experiment B: Design of Synchronous Down Counter Note down your observation in the space provided below for both the cases: i- When CLK input is provided from function generator ii- When CLK input is provided from a switch S0. 12.7 Exercise 1. What is the difference between Up Counter and Down Counter? _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ __________________________________________________________ 2. What is the difference between Synchronous & Asynchronous CIrcuits? _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ __________________________________________________________