Exam Questions for Electronic Engineering Bachelor's Degree - Computer Systems, Exams of Computer Science

Download Exam Questions for Electronic Engineering Bachelor's Degree - Computer Systems and more Exams Computer Science in PDF only on Docsity! Cork Institute of Technology Bachelor of Engineering (Honours) in Electronic Engineering - Stage 3 (EELXE_8_Y3) Spring 2008 COMPUTER SYSTEMS (Time: 3 Hours) Answer any four questions [each 25 marks] Maximum available marks is 100. Use appropriate comments and indentation in program code. PIC and 68000 instruction sets attached. Examiners: Mr. P Cogan Prof. G. Hurley Dr. S. Foley Q1. (a) Describe the operation of the PIC 16F74 microcontroller’s Timer0 module with the help of a diagram (include only the main components). [6 marks] (b) Describe the generation of PWM (Pulse Width Modulation) using the PIC 16F74 with particular reference to resolution, PWM frequency and software versus hardware waveform generation. [6 marks] (c) Write an assembly language program for a PIC 16F74 with a crystal frequency of 4MHz that generates a 5kHz PWM waveform with a 50% duty cycle. [13 marks] continued overleaf …. 2 Q2. (a) Discuss the limitations of the PIC 16F74’s analogue to digital converter and suggest methods for improving its accuracy. [6 marks] (b) Demonstrate how the PIC 16F74 ADC can be used to sample an analogue voltage using an interrupt driven assembly language example. [8 marks] (c) Design a PIC based controller that implements a satellite dish positioning system. The system must move the satellite dish East or West by driving a d.c. motor in either direction. As the motor rotates a switch briefly closes during each revolution, this can be used to determine the position of the satellite dish. Your controller should receive the position to move to using an EIA-232 (RS-232) serial connection. As the dish approaches the correct position its speed should be reduced to avoid overshooting its target. Draw the circuit diagram for your controller on the attached sheet (showing the pinout for the PIC) and give the algorithm for how your software will operate. State any assumptions that you made about the requirements of the design. [11 marks] Q3. (a) What is the Semantic Gap problem? Discuss the two microprocessor design approaches, RISC and CISC and how they approach the Semantic Gap problem. Give examples of modern processors based on each technology. What are the respective advantages of each technology? [8 marks] (b) You have been asked to select the central processing unit for a new line of products. The products are handheld personal digital assistants (PDAs). Discuss which features would be most important in selecting the PDA’s CPU. State which CPU you would select for the product and explain your choice. [8 marks] (c) Write a note on the work carried out by a cache memory controller in a typical computer system. In particular mention any problems that the cache memory controller may have to overcome and explain what is meant by ‘associativity’ and ‘replacement strategy’. [9 marks] continued overleaf …. PIC Special Function Registers — Bank 0 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on: - Address| Name | Bit? | Bite | Bits Bit4 ets | ez | ert | aro | “por oa BOR Bank 0 ooh) [INDE Addressing this location uses contents of FSR to address data memory (not a physical register) oth [THRO Timer) Module Register oan’) [PCL Program Counter (PC) Least Significant Byte oan’ [status ipp_ | RPI | RPO To Pp | z | oe c o4n®) [FSR Indirect Data Memory Address Pointer sh PORTA, — _|__— _[PORTA Data Latch when written: PORTA pins when read oéh___ [PORTE PORTE Data Latch when written: PORTB pins when read a7h__[PORTC PORTE Data Latch when written: PORTC pins when read oh PORTD |PORTD Data Latch when writen: PORTD pins when read oon [PORTE _ _ _ _ — | rez [ ret | REO }oAnit4) | PCLATH _— _— _— Write Buffer for the upper § bits of the Program Counter apn’? _|INTCON GE Pele | TMROIE | INTE RBIE | TMROIF | INTE | RBI och [PIRI PsPIF®| ADE RCIF TXIF sspiF_ | copur | TwR2iF | TMRIF dh | PIR2 = = 7 = = = —__| ccrair och | TMRIL Holding Register for the Least Significant Byte of the 16-bit TMR1 Reaister oh |TMRIH Holding Register for the Mast Significant Byte of the 16-bit TMR1 Register 10h TICON — [| — __[riekpsi] tickpso [Tioscen [ TISYNC | TMRICS [ TMRION Tih [TMR2 Timer? Moclule Register a 12h T2CON —__[Toutps3[Toutps2] TouTPs | TOUTPSO [ TMR2ON | T2CKPS1 | T2CKPSO 1h [SSPBUF [Synchronous Serial Port Receive Buffer/Transmit Register 14h ‘SSPCON woot | sspov [ sspen [ cKP | sspme | sspm2 | sspmi | ssPMmo 15h CCPRIL |Capture/Compare/PWM Register 1 (LSB) Yeh [CCPRIH _ | Capture/Compare/PWM Register1 (MSB} 17h CCPICON = = CCPIX CCP1Y CCPIM2 | CCPIM2 | CCP1M1 | CCP1MO 18h RCSTA SPEN RXx9 SREN CREN = FERR OERR RX9D_ 19h TXREG USART Transmit Data Register tah __[RCREG USART Receive Data Register ABh CCPR2L VM Register2 (LSB) 1ch__[CCPR2H Reaister2 (MSB) 1Dh___[CCP2CON — [| — | cepex | copay | copama [ecp2m2 | copamt | ccp2mo 1éh___ [ADRES [AID Result Register Byte (Fh ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO = - ADON Legend: x= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r= reserved, Shaded locations are unimplemented, read as ‘0' Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transfered to the upper byte of the program counter during branches (CALL or 60 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0 6: This bit always reads as a1 Continued overleaf ... PIC Special Function Registers — Bank 1 , , , , . , . eo | vaueo” | Details Addr Name Bit7 Bité Bits Bit4 Bit3 Bit2 Bit1 BitO POR, Bor | om page Bank 1 0h) |INDF Addressing this location uses contents of FSR to address data memory (not a physical register) [0000 0000] 27, 98 8th [OPTION_REG| RBPU | INTEDG | Tocs | Tose | psa | ps2 | pst | PSO aaa 1121] 20, 44,96 ean [PCL Program Counter’s (PC) Least Significant Byte 000 0000] 26, 95 aan [status rp | rpi | repo | To | PO | z | oc [| C [ovorisex| 10,05 |84hi4) FSR Indirect data memory address pointer xocxx sox] 27, 96 85h TRISA — | — _ [PORTA Data Direction Register =-11 111] 32,95 86h TRISB |PORTB Data Direction Register 4211 1211] 34,6 87h TRISC PORTC Data Direction Register Alli 1111] 35,96 ‘eah) | TRISD IPORTD Data Direction Register ui 111] 36,95 aon [TRISE IBF OBF tsov_[pspmove| — _|PORTE Data Direction Bits ooo -111| 38, 98 sant) |PCLATH = = —__|Write Buffer for the upper 5 bits of the Program Counter =--0 0000] 21,96 apn _[INTCON ce | pee | TMROE | INTE Rie | TMROIF | INTE | RBIF [0000 00x] 23, 98 8Ch |PIE1 PSPIE®) ADIE RCIE TXIE SSPIE CCPIIE | TMR2IE | TMRIIE |o000 oo00} 22,96 Dh |PIE2 = = = = = = — | ccpaie |- 24. 7 gen [PCON = = = = = = Por | sor |- 25,97 arr [— Unimplemented = = 90h \_— Unimplemented = = a [Unimplemented = = 92h IPR2 Timer2 Period Register Alii 1111] 52, 97 93h SSSPADD [Synchronous Serial Port (°C mode) Address Register 9000 0000] 68, 97 34h ISSPSTAT smP [ cKe | DA | P | s | RW [ UA | BF |oo00 oo00] 60,97 95h) — Unimplemented _ _ 6h |— Unimplemented = = 97h = Unimplemented — = 98h TXSTA csrc | 1x9 [| TXEN | Sync | — | BRGH | TRMT | TX9D |ooo0 -o10| 69,97 99h___|SPBRG Baud Rate Generator Register 000 oo00] 71, 97 Ah |— Unimplemented _ 9Bh. i— Unimplemented —_ 9Ch i— Unimplemented = 90h [= Unimplemented = 9Eh i— Unimplemented = 9Fh __[ADCON1 —-7T- J - JT = —__[ pcrc2 [ pcre1 [ PCFGO 84, 7 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’ Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter during branches (CALL or GOTO). 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as '0" 6: This bit always reads as a ‘1’ Continued overleaf ... 7 Configuration Registers for PIC USART Module (From Data Sheet) Continued overleaf … 10 Configuration Registers for PIC PWM (From Data Sheet) PWM period = (PR2 + 1) * 4 * TOSC * (TMR2 prescale value) PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) 11 fe ea imenit-fih- sob fines caSfpderrane’ pera is per <oREASSRAAR fe = ae ee - t. ee np pee 4gge' eagaia5, seer tf reer | og ea aaa 4 te Hs L n= (aaa i ulti nest = = 12