Guide to Using Atmel AVR Microcontroller: ADC and PWM - Prof. Amauri Antonio Arroyo, Study Guides, Projects, Research of Electrical and Electronics Engineering

Download Guide to Using Atmel AVR Microcontroller: ADC and PWM - Prof. Amauri Antonio Arroyo and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity! 1 1 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo Atmel AVR Code A. A. Arroyo University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 2 AVR Studio…. Step 1: Create a New Project Step 2: Configure Project Settings What kind of project we want to create, and setting up filenames and locations. Step 3: Selecting Debugging Platform Select JTAG ICE Select ATmega128 Step 4: Write your code 2 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 3 AVR Studio…. 1. The "Menus" - Windows and AVR Studio specific 2. Toolbars - "shortcuts" to commonly used functions. 3. The Workspace - Files in your Project, IO view, and AVR info 4. The Editor window. 5. The Output Window. Status information is displayed here. 6. The System Tray - information on which mode AVR Studio is in. University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 4 AVR Studio…. 5 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 9 ADC Details The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 10 ADC Details The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. 6 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 11 ADC Details In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register. Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 12 ADC Registers ADCSRA: ADEN Enables ADC ADSC Starts conversion(s) ADIF Conversion complete (an interrupt flag) ADPS2:0 Divides the clock (like in the timer example) ADMUX: A big multiplexer. Tells you which pin you want to do a conversion on. Also lets you select voltage reference. 7 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 13 ADC Registers ADC Multiplexer Selection Register ADMUX University of Florida, EEL 5666 © Dr. A. Antonio Arroyo 14 ADC Registers ADC Control and Status Register ADCSRA 10 19 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo This is a guide to control unhacked servos using Timer1 on the ATMega128. First a little information on servo control: Servos have three input wires: Red = Vcc (between 4.8V and 6V is standard - see your servo data sheet) Black = Ground White = PWM input Servo control is done by sending a pulse width modulation or PWM signal to the PWM input pin. The servo compares that signal to the actual position of the servo and adjusts accordingly. PWM Phase & Freq Correct mode 20 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo PWM Phase & Freq Correct mode The internal circuitry of the servo expects a constant 50Hz PWM signal (a 50 Hz signal is one that repeats every 20 ms). 1/50 Hz = 20 ms The signal you are going to give the servo is one that is high (5V) for 1-2ms and low (0V) for the remainer of the 20ms period. The duration of the high signal determines the position that the servo attempts to maintain. Note that the servo must continually receive this signal in order to maintain its position. 11 21 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo PWM Phase & Freq Correct mode The internal circuitry of the servo expects a constant 50Hz PWM signal (a 50 Hz signal is one that repeats every 20 ms). 1/50 Hz = 20 ms The signal input to the servo is one that is high (5V) for 1-2ms and low (0V) for the remainder of the 20ms period. The duration of the high signal determines the position that the servo attempts to maintain. Note that the servo must continually receive PWM in order to maintain its position. 0.6ms=full left 1.5ms=middle 2.0ms=full right 22 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo PWM Phase & Freq Correct mode Assuming your servo that has 90º of rotation: full left = 0 degrees middle = 45 degrees full right = 90 degrees Different servos have different ranges of rotation so your own full left, middle, and full right maybe correspond to different angles. You may also find that in order to achieve the full range of motion you need to send the servo high pulses longer that 2.0ms or shorter than 1.0ms. Experiment to find what your servo is capable of. 12 23 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo PWM Phase & Freq Correct mode In the Phase & Frequency Correct Mode (PFCM), to generate a 50Hz signal {a high signal that varies between 1-2ms}, we must use Timer 1 or Timer 3 on ATMega128 chip. In PFCM the timer starts at zero, counts up to a user defined value called ICRn (n is the timer number, i.e., Timer 1 or ICR1), and then counts back down to zero. We want the counting up and down process to take 20ms in order to generate the 50Hz signal. To determine the ICR1 value, we need: System clock speed Timer clock speed 24 University of Florida, EEL 5666 © Dr. A. Antonio Arroyo PWM Phase & Freq Correct mode The timer speed is determined by the system clock speed divided by a prescaler. The prescaler is set by the CSn2:0 bits which are located in the TCCRn register (where n is the timer number). For example, Timer1's speed is set by the CS1 bits which are located in TCCR1B register.