Bipolar Junction Transistor, Lecture notes of Electrical and Electronics Engineering

Download Bipolar Junction Transistor and more Lecture notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Chapter 1: Bipolar Junction Transistor (BJT) 1.1 Introduction: On December 23, 1947, however, the electronics industry was to experience the advent of a completely new direction of interest and development. It was on the afternoon of this day that Walter H. Brattain and John Bardeen demonstrated the amplifying action of the first transistor at the Bell Telephone Laboratories. 1.2 Construction and Operation The transistor is a three-layer semiconductor device consisting of either two n- and one p- type layers of material or two p- and one n-type layers of material. Or npn transistor and pnp transistor. Both are shown in Figure 1.1 with the proper dc biasing as it is necessary to establish the proper region of operation for ac amplification. Figure 1.1: PNP and NPN transistors with the proper dc biasing. • The three layers of BJT are called: Emitter (E), Base (B) and Collector (C). • The emitter layer is heavily doped, the base lightly doped, and the collector lightly doped. This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of “free” carriers. 2 • Forward biased B-E Junction in a PNP Transistor; Figure 1.2, the majority carriers (Holes) pass from P to N layer. Figure 1.2: Forward-biased BE junction of a pnp transistor. • Without B-E biased; Figure 1.3 A reverse biased B-C Junction in a PNP Transistor; Flow of minority carriers as indicated in the figure with zero of majority carriers. Figure 1.3: Reverse-biased BC junction of a pnp transistor. In Fig. 1.5 both biasing potentials have been applied to a pnp transistor, a large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material. 5 1.4 Common-Emitter Configuration Figure 1.7: Notation and symbols used with the common-emitter configuration: (a) pnp transistor; (b) npn transistor. Figure 1.8: Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics; (b) base characteristics. 6 𝛽𝑑𝑐 = 𝐼𝐶 𝐼𝐵 𝛽 Ranges from about 50 to 400 𝛽𝑎𝑐 = ∆𝐼𝐶 ∆𝐼𝐵 | 𝑉𝐶𝐸=𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 = ℎ𝑓𝑒(ℎ𝑦𝑏𝑟𝑖𝑑 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑔𝑎𝑖𝑛 𝑓𝑜𝑟 𝐶𝐸 𝑇𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟) 1.5 Common-Collector Configuration Figure 1.9: Notation and symbols used with the common-collector configuration: (a) pnp transistor; (b) npn transistor. • The common collector configuration is used primarily for impedance matching since it has high input impedance and low output impedance, opposite to that of CB (Common Base). The same output characteristics of the CE is used as 𝐼𝐸 ≅ 𝐼𝐶 versus 𝑉𝐶𝐸for different values of 𝐼𝐵. 7 Chapter 2: DC Biasing—BJTs 2.1 Introduction: Basic relations that will be used in this chapter is as follows: 2.2 Operating Point (Q-Point) Point Explanation A Zero current through the device (and zero voltage across it). point A would not be suitable B Good, it is out of cut off or saturation More linear spacing and therefore more linear operation C would allow some positive and negative variation of the output signal, but the peak to- peak value would be limited by the proximity of VCE = 0V/IC = 0 mA. D Point D sets the device operating point near the maximum voltage and power level. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded. 10 The double subscript notations: Example: Determine the following for the fixed-bias configuration of the figure below: (a) IBQ and ICQ. (b) VCEQ. (c) VB and VC. (d) VBC. Solution: 11 2.3.3 Transistor Saturation The term saturation is applied to any system where levels have reached their maximum values. Saturation conditions are normally avoided because the base–collector junction is no longer reverse-biased and the output amplified signal will be distorted. 12 The saturation current: For the previous example the saturation current is: We found ICQ=2.35 mA, which is far from the saturation level and about one-half the maximum value for the design. 2.3.4 Load-Line Analysis The analysis thus far has been performed using a level of _ corresponding with the resulting Q-point. We will now investigate how the network parameters define the possible range of Q- points and how the actual Q-point is determined. The network of Fig. 4.11a establishes an output equation that relates the variables IC and VCE in the following manner: 15 2.4 Emitter-Stabilized Bias Circuit Base-Emitter Loop: Note: Reflected Impedance Collector-Emitter Loop +1Re + Ver t+ Ice — Veo = 0 + R- fic Vee — Veo + Ic(Rc + Re) = 0 ‘ Vee = Vee — Ic(Re + Re) + Ou Ver - - | Vr = TERE + | mg {': Vee = Ve— Vez 7 | Ve = Ver + Ve + Vo = Vee — IcRe Vg = Veo — IpRp Vg = Ver + Ve Example: For the emitter bias network of Fig. 4.22, determine: (a) Ip. (b) Ie. (©) Vee (d) Fe. +40 (e) Ve f @ Vs. se (g) Vee. 410 kQ 3 10 uF 4 1kO Se 40 pr Figure 4.22 Emitter-stabilized bias circuit for Example 4.4 r ¥ 16 17 Saturation level: As VCE=0, So in the previous example the saturation current is: 20 Example: Determine VCE and IC for the following circuit: Example: repeat the previous analysis if β=70 Tc, = Bis = (70)(11.81 pA) = 0.83 mA Ver, = Vee ~ Ie(Re + Re) = 22-V — (0.83 mA)(10 KO + 15 kO) =12.46V Tabulating the results, we have: B Ic, (mA) Ver, V) 140 085 122 70 0.83 12.46 The results clearly show the relative insensitivity of the circuit to the change in £. Even though £ is drastically cut in half, from 140 to 70, the levels of Jc, and Vez, are essentially the same. Example : Determine the ICQ and VCEQ IBV f= Ema Var 3 S1V-O7V__3A1V 5 Rm t+t(B+ DRE 1735kN+(6D02kN) 7855kN = 39.6 pA 21 22 Transistor Saturation: Load line analysis: 2.6 Dc Bias with Voltage Feedback The Base-Emitter loop: Ice = BIg = (7535.5 mA) = 2.66 mA Vo= Vee — eRe = Vee — TeRe = 18 V — (2.66 mA)(3.3 kN) =18V-878V =9.22V Saturation Condition: Voc Ie, = Ie... = —=— Co Come Ret Re Load line analysis: Continuing with the approximation J¢ = J¢ will result in the same load line defined for the voltage-divider and enutter-biased configurations. The level of Zg,, will be de- fined by the chosen bias configuration. Example: In= Vee — Var Rg + BRe _ 20V-07V __193V ~ 680k + (12004.7kO) 1.244 MO = 1551 pA Te, = BIg = (120)(15.51 A) qMcc=20V = 1.86 mA z. $47%0 Vee, = Vee — IcRe ‘5 pe = 20 V — (1.86 mA)(4.7 kO) AA + | eon ¢ = 11.26V WBF Vp = Vor = 0.7 ie—4 p- 10 Cc ) Fe = Fer = 11.26 V Ve=0V + Vac = Vg — Ve =0.7V-11.26V = -10.56V 25 26 2.7 Transistor Switching Circuit: The application of transistors is not limited solely to the amplification of signals. Through proper design it can be used as a switch for computer and control applications. The network of the figure below can be employed as an inverter in computer logic circuitry. Note that the output voltage VC is opposite to that applied to the base or input terminal. In addition, note the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector or output side and for computer applications is typically equal to the magnitude of the “high” side of the applied signal—in this case 5 V. Proper design for the inversion process requires that the operating point switch from cutoff to saturation along the load line depicted in the figure below. We will assume IC=IB=0 and VCE=VCESat=0 When Vi =5 V, the transistor will be “on” and the design must ensure that the network is heavily saturated by a level of IB greater than that associated with the IB curve appearing near the saturation level. In the above figure, this requires that IB =50 mA. The saturation level for the collector current for the circuit of Fig. 4.52a is defined by The level of Jz in the active region just before saturation results can be approxi- mated by the following equation: L C, Bac For the saturation level we must therefore ensure that the following condition 1s satisfied: Is... = Te Inp> Ba (4.46) For the network of Fig. 4.52b, when FV; = 5 V, the resulting level of J, is the fol- lowing: F,-0.7V _5V—-07V I=, A Veo 5 and Io. = Re = Jak 6.1 mA Testing Eq. (4.46) gives Te Ip= 63 wA > G= = SOA — 49.8 pa Fee Rest = Te Using a typical average value of Vez, such as 0.15 V gives _Vee, 0.15V Tc, 6.1 mA Rest = 2460 For V, = 0 V, as shown in Fig. 4.54, the cutoff condition will result in a resistance level of the followmg magnitude: Vee _ 5V =f * no Reso Tazo OmA resulting in the open-circuit equivalence. For a typical value of I¢zo = 10 mA, the magnitude of the cutoff resistance is which certainly approaches an open-circuit equivalence for many situations. 27