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Building an ALU to Support MIPS Instructions: Integer Arithmetic, Study notes of Computer Architecture and Organization

The process of building an arithmetic logic unit (alu) to support integer arithmetic instructions, specifically andi, ori, add, subtract, and set-on-less-than (slt), for the mips instruction set. The design of a 1-bit alu and its expansion into a 32-bit alu using multiplexers and various logic gates. It also discusses the use of two's complement for subtraction and the implementation of slt and test for equality instructions.

Typology: Study notes

Pre 2010

Uploaded on 02/12/2009

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Download Building an ALU to Support MIPS Instructions: Integer Arithmetic and more Study notes Computer Architecture and Organization in PDF only on Docsity! 1 Chapter Three: Building an ALU to support MIPS integer arithmetic (Material from Appendix B.5 on CD-ROM) 2 • Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true • Show the truth table for these three functions. • Show the Boolean equations for these three functions. • Show an implementation consisting of inverters, AND, and OR gates. See Appendix B of textbook (on CDROM) Review: Boolean Algebra & Gates 3 • Let's build an ALU to support the andi and ori instructions – we'll just build a 1 bit ALU, and use 32 of them • Possible Implementation (sum-of-products): b a operation result op a b res An ALU (arithmetic logic unit) 4 • Selects one of the inputs to be the output, based on a control input • Lets build our ALU using a MUX: S C A B 0 1 Review: The Multiplexor note: we call this a 2-input mux even though it has 3 inputs! 9 • Need to support the set-on-less-than instruction (slt) – remember: slt is an arithmetic instruction – produces a 1 if rs < rt and 0 otherwise – use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) – use subtraction: (a-b) = 0 implies a = b Tailoring the ALU to the MIPS Supporting slt Use this ALU for most significant bit (bit 31) Use this ALU for bits 0-30 11 Supporting slt 12 Test for equality • Notice control lines: 0000 = and 0001 = or 0010 = add 0110 = subtract 0111 = slt 1100 = nor •Note: zero is a 1 when the result is zero! 13 Conclusion • We can build an ALU to support the MIPS instruction set – key idea: use multiplexor to select the output we want – we can efficiently perform subtraction using two’s complement – we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware – all of the gates are always working – the speed of a gate is affected by the number of inputs to the gate – the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • Our primary focus: comprehension, however, – Clever changes to organization can improve performance (similar to using better algorithms in software) – we’ll look next at multiplication
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