Buses - Computer Architecture - Slides | CSCI 4717, Study notes of Computer Architecture and Organization

Download Buses - Computer Architecture - Slides | CSCI 4717 and more Study notes Computer Architecture and Organization in PDF only on Docsity! 1 Buses – Page 1CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Buses Reading: Stallings, Sections 3.4, 3.5, and 7.7 Buses – Page 2CSCI 4717 – Computer Architecture Buses – Common Characteristics • Multiple devices communicating over a single set of wires • Only one device can talk at a time or the message is garbled • Each line or wire of a bus can at any one time contain a single binary digit. Over time, however, a sequence of binary digits may be transferred • These lines may and often do send information in parallel • A computer system may contain a number of different buses Buses – Page 3CSCI 4717 – Computer Architecture Buses – Structure • Serial versus parallel • Around 50-100 lines although it's possible to have as few as 3 or 4 • Lines can be classified into one of four groups – Data lines – Address Lines – Control Lines – Power Buses – Page 4CSCI 4717 – Computer Architecture Buses – Structure (continued) • Bus lines (parallel) – Data – Address – Control – Power • Bus lines (serial) – Data, address, and control are sequentially sent down single wire – There may be additional control lines – Power Buses – Page 5CSCI 4717 – Computer Architecture Buses – Structure (continued) • Data Lines – Passes data back and forth – Number of lines represents width • Address lines – Designates location of source or destination – Width of address bus specifies maximum memory capacity – High order selects module and low order selects a location within the module Buses – Page 6CSCI 4717 – Computer Architecture Bus Structure – Control lines • Because multiple devices communicate on a line, control is needed • Timing • Typical lines include: – Memory Read or Write – I/O Read or Write – Transfer ACK – Bus request – Bus grant – Interrupt request – Interrupt acknowledgement – Clock – Reset 2 Buses – Page 7CSCI 4717 – Computer Architecture Operation – Sending Data • Obtain the use of the bus • Transfer the data via the bus • Possible acknowledgement Buses – Page 8CSCI 4717 – Computer Architecture Operation – Requesting Data • Obtain the use of the bus • Transfer the data request via the bus • Wait for other module to send data • Possible acknowledgement Buses – Page 9CSCI 4717 – Computer Architecture Classic Bus Arrangement • All components attached to bus (STD bus) • Due to Moore's law, more and more functionality exists on a single board, so major components are now on same board or even the same chip Buses – Page 10CSCI 4717 – Computer Architecture Physical Implementations • Parallel lines on circuit boards (ISA or PCI) • Ribbon cables (IDE) Buses – Page 11CSCI 4717 – Computer Architecture Physical Implementations (continued) • Strip connectors on mother boards (PC104) • External cabling (USB or Firewire) Buses – Page 12CSCI 4717 – Computer Architecture Single Bus Problems Lots of devices on one bus leads to: • Physically long buses – Propagation delays – Long data paths mean that co- ordination of bus use can adversely affect performance – Reflections/termination problems • Aggregate data transfer approaches bus capacity • Slower devices dictate the maximum bus speed 5 Buses – Page 25CSCI 4717 – Computer Architecture Synchronous Bus Timing Buses – Page 26CSCI 4717 – Computer Architecture Asynchronous Timing • Devices must have certain tolerances to provide responses to signal stimuli • More flexible allowing slower devices to communicate on same bus with faster devices. • Performance of faster devices, however, is limited to speed of bus Buses – Page 27CSCI 4717 – Computer Architecture Asynchronous Timing – Read Buses – Page 28CSCI 4717 – Computer Architecture Asynchronous Timing – Write Buses – Page 29CSCI 4717 – Computer Architecture Bus Width • Wider the bus the better the data transfer rate or the wider the addressable memory space • Serial “width” is determined by length/duration of frame Buses – Page 30CSCI 4717 – Computer Architecture Peripheral Component Interconnection (PCI) Bus Brief history • Original PC came out with 8-bit ISA bus which was slow, but had enormous amount of existing equipment. • For AT, IBM expanded ISA bus to 16-bit by adding connector • Many PC board manufacturers started making higher speed, proprietary buses • Intel released the patents to its PCI and this soon took over as the standard 6 Buses – Page 31CSCI 4717 – Computer Architecture PCI Bus (continued) Brief list of PCI 2.2 characteristics • General purpose • Mezzanine or peripheral bus • Supports single- and multi-processor architectures • 32 or 64 bit – multiplexed address and data • Synchronous timing • Centralized arbitration (requires bus controller) • 49 mandatory lines (see Table 3.3) Buses – Page 32CSCI 4717 – Computer Architecture Required PCI Bus Lines (Table 3.3) • Systems lines – clock and reset • Address & Data – 32 time multiplexed lines for address/data – Parity lines • Interface Control – Hand shaking lines between bus controller and devices – Selects devices – Allows devices to indicates when they are ready Buses – Page 33CSCI 4717 – Computer Architecture Required PCI Bus Lines (continued) • Arbitration – Not shared – Direct connection to PCI bus arbiter • Error lines – parity and critical/system Buses – Page 34CSCI 4717 – Computer Architecture Optional PCI Bus Lines There are 51 optional PCI 2.2 bus lines • Interrupt lines – Not shared – Multiple lines for multiple interrupts on a single device • Cache support • 64-bit Bus Extension – Additional 32 lines – Time multiplexed – 2 lines to enable devices to agree to use 64-bit transfer • JTAG/Boundary Scan – For testing procedures Buses – Page 35CSCI 4717 – Computer Architecture PCI Commands • Transaction between initiator (master) and target • Master claims bus • During address phase of write, 4 C/BE lines signal the transaction type • One or more data phases Buses – Page 36CSCI 4717 – Computer Architecture PCI Transaction Types • Interrupt acknowledge – prompts identification from interrupting device • Special cycle – message broadcast • I/O read – read to I/O address space • I/O write – write to I/O address space • Memory read – 1 or 2 data transfer cycles • Memory read line – 3 to 12 data transfer cycles • Memory read multiple – more than 12 data transfers 7 Buses – Page 37CSCI 4717 – Computer Architecture PCI Transaction Types (continued) • Memory write – writing 1 or more cycles to memory • Memory write and invalidate – writing 1 or more cycles to memory allowing for cache write-back policy • Configuration read – reading PCI device's configuration (up to 256 configuration registers per device) • Configuration write – writing PCI device's configuration (up to 256 configuration registers per device) • Dual address cycle – indication of 64-bit addressing on 32 bit lines Buses – Page 38CSCI 4717 – Computer Architecture PCI Read Timing Diagram Buses – Page 39CSCI 4717 – Computer Architecture PCI Bus Arbiter Buses – Page 40CSCI 4717 – Computer Architecture PCI Bus Arbitration Between Two Masters Buses – Page 41CSCI 4717 – Computer Architecture Higher Performance External Buses • Historically, parallel has been used for high speed peripherals (e.g., SCSI, parallel port zip drives rather than serial port). High speed serial, however, has begun to replace this need • Serial communication also used to be restricted to point-to-point communications. Now there's an increasing prevalence of multipoint Buses – Page 42CSCI 4717 – Computer Architecture IEEE 1394 FireWire • Inexpensive alternative needed for SCSI • High performance serial bus • Serial implies cheaper cabling (fewer wires, less shielding, less synchronization) • Small connectors for smaller devices • Fast • Low cost • Easy to implement • Also being used in digital cameras, VCRs and TVs