cache_basics deals with cache mappings , direct associative, set associative, Lecture notes of Advanced Computer Architecture

Download cache_basics deals with cache mappings , direct associative, set associative and more Lecture notes Advanced Computer Architecture in PDF only on Docsity! REG CACHE MAIN SECONDARY MEMORY HIERARCHY Cache • Small amount of fast memory • Sits between normal main memory and CPU Direct Mapping • Each block of main memory maps to only one cache line – i.e. if a block is in cache, it must be in one specific place • Address is in two parts • Least Significant w bits identify unique word • Most Significant s bits specify one memory block • The MSBs are split into a cache line field r and a tag of s-r (most significant) Direct Mapping Address Structure Tag s-r Line or Slot r Word w 8 14 2 • 24 bit address • 2 bit word identifier (4 byte block) • 22 bit block identifier – 8 bit tag (=22-14) – 14 bit slot or line • No two blocks in the same line have the same Tag field • Check contents of cache by finding line and checking Tag Direct Mapping Cache Organization Main Memory Memory Address wo WI Tag Line Word W2 Wi W4j Widj+) Wi4i+2) Wi 4dj+3) Compare (hit in cache} I . . I . i! I . To (miss in cache} Fully Associative Cache Organization Main Memory WO Wi 7 Bo Wa Memory Address Tag Word W4i Wi4j+l) Wi4j4+2) Wi4j+3) Compare (hit in cache) 8 (miss in cache}. Tag 22 bit Word 2 bit Associative Mapping Address Structure • 22 bit tag stored with each 32 bit block of data • Compare tag field with tag entry in cache to check for hit Set Associative Mapping • Cache is divided into a number of sets • Each set contains a number of lines • A given block maps to any line in a given set – e.g. Block B can be in any line of set i • e.g. 2 lines per set – 2 way associative mapping – A given block can be in one of 2 lines in only one set