Carry Save Adder Trees in Multipliers - Lecture Notes | ECEN 6263, Study notes of Electrical and Electronics Engineering

Download Carry Save Adder Trees in Multipliers - Lecture Notes | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nCarry Save Adder Trees in Multipliers A naive organization for adding the partial products together in an array multiplier is to accumulate the partial products in each row and pass the accumulated partial products (using carry save adders) to the next row This makes the total delay going through the carry save proportional to N, the number of bits in the data words (there are N rows or N/2 rows if Booth recoding is used.) This delay is too long if we use a fast adder for the last row which as delay ~ log N. The easiest way to reduce the CSA delay is to make a tree structure instead of the linearly connected naive design. In general, we want an efficient way to add N (or N/2) partial products. Let us examine the problem of adding 1 bit of each of the N products (this is called a “bit-slice”. Example 4 partial products (8x8 Booth) PPG PPG PPG PPG CSA CSA CSA to fast adder CSA CSA PP4i PP1iPP2iPP3iCarry Save Adder Trees in Multipliers November 3, 1999 page 1 of 8 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nThe horizontal lines indicate that the carry out must be passed to the next most significant bit slice. Since we make each bit slice the same, there will also be a corresponding carry- in. A tree of carry save adders is called a “Wallace tree”. Note that only 2 levels of CSA’ are needed in the Wallace tree for 4 partial products whereas the linear structure requires 3 levels. There is an even greater savings for larger multipliers. For example 8 partial prod- ucts (16x16 Booth) We have now used a notation where the CSA is regarded as a general element adding three inputs and putting out two binary weighted outputs. Thus, the (4,2) element is simply the design we already did for the 4 partial product example with four equally weighted inputs and two binary weighted outputs. The (4,2) element has recently become a popular build- ing block for CSA trees. This is because there are 1/2 as many outputs as inputs to the (4,2) element. Thus, binary trees may be constructed which make the layout problem somewhat easier. 3,2 PP5iPP8i PP7i PP6i PP4i PP3i PP2i PP1i 3,2 3,2 3,2 4,2 to fast adderCarry Save Adder Trees in Multipliers November 3, 1999 page 2 of 8 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n C arry S ave A dder T rees in M ultipliers N ovem ber 3, 1999 page 5 of 8 For exam ple (16,2) out of (7,3) blocks. PP4i PP3i PP2i PP1i 7,3 2 1 shift 1 s hift 2PP16i PP15i PP14i PP13i PP12i PP11i PP10i PP9i PP8i PP7i PP6i PP5i 7,3 7,3 4,2 shift shift            E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nSuch a diagram is much harder to draw out of (3,2) blocks, and the routing is correspond- ingly more complicated. Use of the (7,3) block organizes the routing and makes it more efficient even if the (7,3) block is constructed from (3,2) blocks! (More on this later). A similar organization is obtained using (15,4) as a building block. However, it is difficult to easily route the 15 inputs to this single block (it requires numerous feed throughs in the partial product generator!). The number of inputs can be reduced by making some of the inputs have higher binary weight. For example, a (5,5,4) block is an alternative to the (15,4) block. The (5,5,4) block requires 50% less feed throughs than the (15,4) block. One might try to implement the large building blocks by developing logic equations for each output and synthesizing the corresponding logic gates. This results is complex logic functions with a high fan out from the circuit inputs (the same input occurs in many differ- ent terms of the logic equation). This causes the implementation to be too slow and take up too much area. The estimated the no. of FET’s ~ (no. of inputs)4! It seems more effi- cient to implement the larger building blocks out of smaller building blocks. If this pro- cess is repeated for the smaller blocks, then ultimately all the blocks can be made from the (3,2) element. For example            weight 1 15,4 weight 2       weight 1 5,5,4 wt8 wt4 wt2 wt1wt8 wt4 wt2 wt1 3,2 3,2 (2) (1) (2) (1) wt4 wt2 wt1 (7,3) 3,2 3,2 (2) (2) (4) (1) Internal wiring keeps track of proper binary weightCarry Save Adder Trees in Multipliers November 3, 1999 page 6 of 8 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g nWe still gain efficiency in the design by using the (7,3) block since it 1. simplifies global routing 2. allows re-use of the layout and routing already done for the (7,3) when multiple (7,3) are used. The higher order building blocks discussed so far do not have any “hidden” carries like the (4,2) block discussed earlier. It is also possible to make higher order blocks with “hidden” carry-outs that do not depend on the “hidden” carry-ins. A (6,2) block and a (9,2) block can be made. This idea can be extended to arbitrarily large blocks. Note that none of the carries “ripple” across from right to left. Rather the carries propagate down and to the left. 3,23,2 4,2 (6,2) 3,2 3,23,2 6,2 (9,2)Carry Save Adder Trees in Multipliers November 3, 1999 page 7 of 8