chapter 04 solution, microelectronic circuits, Exercises of Electronics

Download chapter 04 solution, microelectronic circuits and more Exercises Electronics in PDF only on Docsity! SEDRA-ISM: “E-CH04” — 2014/11/12 — 11:02 — PAGE 1 — #1 Exercise 4–1 Ex: 4.1 Refer to Fig. 4.3(a). For v I ≥ 0, the diode conducts and presents a zero voltage drop. Thus vO = v I . For v I < 0, the diode is cut off, zero current flows through R, and vO = 0. The result is the transfer characteristic in Fig. E4.1. Ex: 4.2 See Fig. 4.3a and 4.3b. During the positive half of the sinusoid, the diode is forward biased, so it conducts resulting in vD = 0. During the negative half cycle of the input signal v I , the diode is reverse biased. The diode does not conduct, resulting in no current flowing in the circuit. So vO = 0 and vD = v I − vO = v I . This results in the waveform shown in Fig. E4.2. Ex: 4.3 îD = v̂ I R = 10 V 1 k = 10 mA dc component of vO = 1 π v̂O = 1 π v̂ I = 10 π = 3.18 V Ex: 4.4 (a) 5 V V  0 V  2 mAI 2.5 k 5  0 2.5   (b) 5 V V  5 V I  0 A2.5 k   (c) 5 V V  5 V I  0 A   2.5 k (d) 5 V V  0 V 0  5 2.5 I    2.5 k 2 mA (e) V  3 V 3 V 2 V 1 V 3 1 I  1 k  3 mA 0 0 I (f) 3 V 2 V 1 V I  1 k 5 V 0 0 I V  1 V  4 mA 5  1 1   Ex: 4.5 Vavg = 10 π 50+ R = 10 π 1 mA = 10 π k ∴ R = 3.133 k SEDRA-ISM: “E-CH04” — 2014/11/12 — 11:02 — PAGE 2 — #2 Exercise 4–2 Ex: 4.6 Equation (4.5) V2 − V1 = 2.3 V T log ( I2 I1 ) At room temperature VT = 25 mV V2 − V1 = 2.3× 25× 10−3 × log ( 10 0.1 ) = 115 mV Ex: 4.7 i = ISev/VT (1) 1 (mA) = ISe0.7/VT (2) Dividing (1) by (2), we obtain i (mA) = e(v−0.7)/VT ⇒ v = 0.7+ 0.025 ln(i) where i is in mA. Thus, for i = 0.1 mA, v = 0.7+ 0.025 ln(0.1) = 0.64 V and for i = 10 mA, v = 0.7+ 0.025 ln(10) = 0.76 V Ex: 4.8 T = 125− 25 = 100◦C IS = 10−14 × 1.15T = 1.17× 10−8A Ex: 4.9 At 20◦C I = 1 V 1 M = 1 μA Since the reverse leakage current doubles for every 10◦C increase, at 40◦C I = 4× 1 μA = 4 μA ⇒ V = 4 μA × 1 M = 4.0 V @ 0◦C I = 1 4 μA ⇒ V = 1 4 × 1 = 0.25 V Ex: 4.10 a. Use iteration: Diode has 0.7 V drop at 1 mA current. Assume VD = 0.7 V ID = 5− 0.7 10 k = 0.43 mA Use Eq. (4.5) and note that V1 = 0.7 V, I1 = 1 mA ID VCC  5 V VD R  10 k   V2 − V1 = 2.3× VT log ( I2 I1 ) V2 = V1 + 2.3× VT log ( I2 I1 ) First iteration V2 = 0.7+ 2.3× 25× 10−3 log ( 0.43 1 ) = 0.679 V Second iteration I2 = 5− 0.679 10 k = 0.432 mA V2 = 0.7+ 2.3× 25.3× 10−3 log ( 0.432 1 ) = 0.679 V  0.68 V we get almost the same voltage. ∴ The iteration yields ID = 0.43 mA, VD = 0.68 V b. Use constant voltage drop model: VD = 0.7 V constant voltage drop ID = 5− 0.7 10 k = 0.43 mA Ex: 4.11 RI 10 V 2.4 V   Diodes have 0.7 V drop at 1 mA ∴ 1 mA = ISe0.7/VT (1) At a current I(mA), I = ISeVD/VT (2) Using (1) and (2), we obtain I = e(VD−0.7)/VT SEDRA-ISM: “E-CH04” — 2014/11/12 — 11:02 — PAGE 5 — #5 Exercise 4–5 Ex: 4.18 15 V 200  Thus, at no load VZ 5.1 V   VZ 15  5.1 0.2 k I   49.5 mA 50 mA For line regulation: 200  7 vi vo  Line regulation = vo v i = 7 200+ 7 = 33.8 mV V For load regulation: 200  VZ0 VO rZ IL V O IL = −IL(rZ ‖ 200 ) IL mA = −6.8 mV mA Ex: 4.19  vS VD 2 t Vs  12 2 0 uu a. The diode starts conduction at vS = VD = 0.7 V vS = Vs sin ωt, here Vs = 12 √ 2 At ωt = θ , vS = Vs sin θ = VD = 0.7 V 12 √ 2 sin θ = 0.7 θ = sin−1 ( 0.7 12 √ 2 )  2.4◦ Conduction starts at θ and stops at 180− θ . ∴ Total conduction angle = 180− 2θ = 175.2◦ b. vO,avg = 1 2π (π−θ)∫ θ (Vs sin φ − VD) dφ = 1 2π [−Vs cos φ − VDφ]φ=π−θφ−θ = 1 2π [Vs cos θ − Vs cos (π − θ)− VD (π − 2θ)] But cos θ  1, cos (π − θ)  − 1, and π − 2θ  π vO,avg = 2Vs 2π − VD 2 = Vs π − VD 2 For Vs = 12 √ 2 and VD = 0.7 V vO,avg = 12 √ 2 π − 0.7 2 = 5.05 V c. The peak diode current occurs at the peak diode voltage. ∴ îD = Vs − VD R = 12 √ 2− 0.7 100 = 163 mA PIV = +V S = 12 √ 2  17 V Ex: 4.20 ( )  vS Vs VS   VD output 0 input t a. As shown in the diagram, the output is zero between (π − θ) to (π + θ) = 2θ SEDRA-ISM: “E-CH04” — 2014/11/12 — 11:02 — PAGE 6 — #6 Exercise 4–6 Here θ is the angle at which the input signal reaches VD. ∴ Vs sin θ = VD θ = sin−1 ( VD Vs ) 2θ = 2 sin−1 ( VD Vs ) b. Average value of the output signal is given by VO = 1 2π ⎡ ⎣2× (π−θ)∫ θ (Vs sin φ − VD) dφ ⎤ ⎦ = 1 π [−Vs cos φ − VDφ]π−θφ=θ  2 Vs π − VD, for θ small. c. Peak current occurs when φ = π 2 . Peak current = Vs sin (π /2)− VD R = Vs − VD R If vS is 12 V(rms), then Vs = √ 2× 12 = 12√2 Peak current = 12 √ 2− 0.7 100  163 mA Nonzero output occurs for angle = 2 (π − 2θ) The fraction of the cycle for which vO > 0 is = 2 (π − 2θ) 2π × 100 = 2 [ π − 2 sin−1 ( 0.7 12 √ 2 )] 2π × 100  97.4 % Average output voltage VO is VO = 2 Vs π − VD = 2× 12 √ 2 π − 0.7 = 10.1 V Peak diode current îD is îD = Vs − VD R = 12 √ 2− 0.7 100 = 163 mA PIV = Vs − VD + VS = 12√2− 0.7+ 12√2 = 33.2 V Ex: 4.21 Vs Vs  sin–1  2VD output 0 2VD VS input t (a) VO,avg = 1 2π ∫ (Vs sin φ − 2VD) dφ = 2 2π [−Vs cos φ − 2VDφ]π−θφ=θ = 1 π [Vs cos φ − Vs cos(π − θ)− 2VD(π − 2θ)] But cos θ ≈ 1, cos (π − θ) ≈ − 1 π − 2θ ≈ π . Thus ⇒ VO,avg  2Vs π − 2VD = 2× 12 √ 2 π − 1.4 = 9.4 V (b) Peak diode current = Peak voltage R = Vs − 2VD R = 12 √ 2− 1.4 100 = 156 mA PIV = Vs − VD = 12 √ 2− 0.7 = 16.3 V Ex: 4.22 Full-wave peak rectifier: R C   vO vS   vS D1 D2 Vp Vr assume ideal diodes t t { T 2 The ripple voltage is the amount of voltage reduction during capacitor discharge that occurs SEDRA-ISM: “E-CH04” — 2014/11/12 — 11:02 — PAGE 7 — #7 Exercise 4–7 when the diodes are not conducting. The output voltage is given by vO = Vpe−t/RC Vp − Vr = Vpe− T/2RC ← discharge is only half the period. We also assumed t T 2 . Vr = Vp ( 1− e− T/2RC ) e− T/2 RC  1− T/2 RC , for CR T/2 Thus Vr  Vp ( 1− 1+ T/2 RC ) Vr = Vp 2fRC (a) Q.E.D. To find the average diode current, note that the charge supplied to C during conduction is equal to the charge lost during discharge. QSUPPLIED = QLOST iCavt = CV r SUB (a) ( iD,av − IL ) t = C Vp 2fRC = Vp 2fR = Vpπ ωR iD,av = Vpπ ωtR + IL where ωt is the conduction angle. Note that the conduction angle has the same expression as for the half-wave rectifier and is given by Eq. (4.30), ωt ∼= √ 2Vr Vp (b) Substituting for ωt, we get ⇒ iD,av = πVp√ 2Vr Vp · R + IL Since the output is approximately held at Vp, Vp R ≈ IL · Thus ⇒ iD,av ∼= π IL √ Vp 2Vr + IL = IL [ 1+ π √ Vp 2Vr ] Q.E.D. If t = 0 is at the peak, the maximum diode current occurs at the onset of conduction or at t = −ωt. During conduction, the diode current is given by iD = iC + iL iD,max = C dvS dt ∣∣∣∣ t=−ωt + iL assuming iL is const. iL  Vp R = IL = C d dt ( Vp cos ωt )+ IL = −C sin ω t × ωVp + IL = −C sin(−ωt)× ωVp + IL For a small conduction angle sin(−ωt) ≈ − ωt. Thus ⇒ iD,max = Cωt × ωVp + IL Sub (b) to get iD,max = C √ 2V r Vp ωVp + IL Substituting ω = 2π f and using (a) together with Vp/R  IL results in iDmax = IL [ 1+ 2π √ Vp 2Vr ] Q.E.D. Ex: 4.23    vS vO D2 D1 D3 D4 C R ac line voltage The output voltage, vO, can be expressed as vO = ( Vp − 2VD ) e−t/RC At the end of the discharge interval vO = Vp − 2VD − Vr The discharge occurs almost over half of the time period  T/2. For time constant RC T 2 SEDRA-ISM: “P-CH04-001-013” — 2014/11/12 — 15:18 — PAGE 1 — #1 Chapter 4–1 4.1 I   VD1.5 V 1  (a) (b) I   VD1.5 V 1  (a) The diode is reverse biased, thus I = 0 A VD = −1.5 V (b) The diode is forward biased, thus VD = 0 V I = 1.5 V 1  = 1.5 A 4.2 Refer to Fig. P4.2. (a) Diode is conducting, thus V = −3 V I = +3− (−3) 10 k = 0.6 mA (b) Diode is reverse biased, thus I = 0 V = +3 V (c) Diode is conducting, thus V = +3 V I = +3− (−3) 10 k = 0.6 mA (d) Diode is reverse biased, thus I = 0 V = −3 V 4.3 (a) 2 k 2 k I  Cutoff Conducting D1 D2 3 V 1 V 2 V V  2 V  2.5 mA 2 (3) (b) 2 k 2 Cutoff Conducting D1 D2 3 V 1 V 2 V V  1 V  1 mA 3 (1) I  4.4 (a) 5 V 0 t vO V p+ = 5 V Vp− = 0 V f = 1 kHz (b) 5 V 0 t vO Vp+ = 0 V Vp− = −5 V f = 1 kHz SEDRA-ISM: “P-CH04-001-013” — 2014/11/12 — 15:18 — PAGE 2 — #2 Chapter 4–2 (c) t0 vO vO = 0 V Neither D1 nor D2 conducts, so there is no output. (d) 5 V t vO Vp+ = 5 V, Vp− = 0 V, f = 1 kHz Both D1 and D2 conduct when v I > 0 (e) 5 V 5 V t vO Vp+ = 5 V, Vp− = −5 V, f = 1 kHz D1 conducts when v I > 0 and D2 conducts when v I < 0. Thus the output follows the input. (f) 5 V t vO Vp+ = 5 V, Vp− = 0 V, f = 1 kHz D1 is cut off when v I < 0 (g) 5 V t vO Vp+ = 0 V, Vp− = −5 V, f = 1 kHz D1 shorts to ground when v I > 0 and is cut off when v I < 0 whereby the output follows v I . (h) t vO  0 V vO = 0 V∼ The output is always shorted to ground as D1 conducts when v I > 0 and D2 conducts when v I < 0. (i) 5 V t vO 2.5 V Vp+ = 5 V, Vp− = −2.5 V, f = 1 kHz When v I > 0, D1 is cut off and vO follows v I . When v I < 0, D1 is conducting and the circuit becomes a voltage divider where the negative peak is 1 k 1 k+ 1 k ×−5 V = −2.5 V (j) 2.5 V 5 V t vO Vp+ = 5 V, Vp− = −2.5 V, f = 1 kHz When v I > 0, the output follows the input as D1 is conducting. When v I < 0, D1 is cut off and the circuit becomes a voltage divider. (k) 5 V 5 V 1 V t vO 4 V Vp+ = 1 V, Vp− = −4 V, f = 1 kH3 When v I > 0, D1 is cut off and D2 is conducting. The output becomes 1 V. When v I < 0, D1 is conducting and D2 is cut off. The output becomes: vO = v I + 1 V SEDRA-ISM: “P-CH04-001-013” — 2014/11/12 — 15:18 — PAGE 3 — #3 Chapter 4–3 4.5 From Fig. P4.5 we see that when v I < VB; that is, v I < 3 V, D1 will be conducting the current I and iB will be zero. When v I exceeds the battery voltage (3 V), D1 cuts off and D2 conducts, thus steering I into the battery. Thus, iB will have the waveform shown in the figure. Its peak value will be 60 mA. To obtain the average value, we first determine the conduction angle of D2, (π − 2θ), where θ = sin−1 ( 3 6 ) = 30◦ Thus π − 2θ = 180◦ − 60 = 120◦ The average value of iB will be iB|av = 60× 120 ◦ 360◦ = 20 mA If the peak value of v I is reduced by 10%, i.e. from 6 V to 5.4 V, the peak value of iB does not change. The conduction angle of D2, however, changes since θ now becomes θ = sin−1 ( 3 5.4 ) = 33.75◦ and thus π − 2θ = 112.5◦ Thus the average value of iB becomes iB|av = 60× 112.5 ◦ 360◦ = 18.75 mA 4.6 A B X Y 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 1 X = AB, Y = A+ B X and Y are the same for A = B X and Y are opposite if A = B 4.7 The case for the highest current in a single diode is when only one input is high: VY = 5 V VY R ≤ 0.2 mA⇒ R ≥ 25 k 4.8 The maximum input current occurs when one input is low and the other two are high. 5− 0 R ≤ 0.2 mA R ≥ 25 k 4.9 (a) 3 V 3 V 12 k 0.33 mA 0.33 mA I  0 D2 ON D1 OFF 1 V V  1 V 6 k (a) If we assume that both D1 and D2 are conducting, then V = 0 V and the current in D2 will be [0− (−3)]/6 = 0.5 mA. The current in the 12 k will be (3− 0)/12 = 0.25 mA. A node equation at the common anodes node yields a negative current in D1. It follows that our assumption is wrong and D1 must be off. Now making the assumption that D1 is off and D2 is on, we obtain the results shown in Fig. (a): I = 0 V = −1 V SEDRA-ISM: “P-CH04-014-030” — 2014/11/12 — 15:20 — PAGE 6 — #2 Chapter 4–6 Thus VT = 8.62× 10−5 × (273× x◦C), V x [◦C] VT [mV] −55 18.8 0 23.5 +55 28.3 +125 34.3 for VT = 25 mV at 17◦C 4.18 i = I Sev/0.025 ∴ 10,000IS = IS ev/0.025 v = 0.230 V At v = 0.7 V, i = IS e0.7/0.025 = 1.45× 1012IS 4.19 I1 = IS e0.7/VT = 10−3 i2 = ISe0.5/VT i2 i1 = i2 10−3 = e 0.5− 0.70.025 i2 = 0.335 μA 4.20 I = ISeVD/VT 10−3 = ISe0.7/VT (1) For VD = 0.71 V, I = ISe0.71/VT (2) Combining (1) and (2) gives I = 10−3e(0.71− 0.7)/0.025 = 1.49 mA For VD = 0.8 V, I = ISe0.8/VT (3) Combining (1) and (3) gives I = 10−3 × e(0.8− 0.7)/0.025 = 54.6 mA Similarly, for VD = 0.69 V we obtain I = 10−3 × e(0.69− 0.7)/0.025 = 0.67 mA and for VD = 0.6 V we have I = 10−3e(0.6− 0.7)/0.025 = 18.3 μA To increase the current by a factor of 10, VD must be increased by VD, 10 = eVD/0.025 ⇒ VD = 0.025 ln10 = 57.6 mV 4.21 IS can be found by using IS = ID · e−VD/VT . Let a decrease by a factor of 10 in ID result in a decrease of VD by V: ID = ISeVD/VT ID 10 = ISe(VD−V)/VT = ISeVD/VT · e−V /V T Taking the ratio of the above two equations, we have 10 = eV /V T ⇒ V  60 mV Thus the result in each case is a decrease in the diode voltage by 60 mV. (a) VD = 0.700 V, ID = 1 A ⇒ IS = 6.91× 10−13 A; 10% of ID gives VD = 0.64 V (b) VD = 0.650 V, ID = 1 mA ⇒ IS = 5.11× 10−15 A; 10% of ID gives VD = 0.59 V (c) VD = 0.650 V, ID = 10 μA ⇒ IS = 5.11× 10−17 A; 10% of ID gives VD = 0.59 V (d) VD = 0.700 V, ID = 100 mA ⇒ IS = 6.91× 10−14 A; 10% of ID gives VD = 0.64 V 4.22 IS can be found by using IS = ID · e−VD/VT . Let an increase by a factor of 10 in ID result in an increase of VD by V: ID = IS eVD/VT 10ID = IS e(VD+V )/VT = IS eVD/VT · eV /V T Taking the ratio of the above two equations, we have 10 = eV /V T ⇒ V  60 mV Thus the result is an increase in the diode voltage by 60 mV. Similarly, at ID/10, VD is reduced by 60 mV. SEDRA-ISM: “P-CH04-014-030” — 2014/11/12 — 15:20 — PAGE 7 — #3 Chapter 4–7 (a) VD = 0.70 V, ID = 10 mA ⇒ IS = 6.91× 10−15 A; ID × 10 gives V D = 0.76 V ID/10 gives VD = 0.64 V (b) VD = 0.70 V, ID = 1 mA ⇒ IS = 6.91× 10−16 A; ID × 10 gives V D = 0.76 V ID/10 gives VD = 0.64 V (c) VD = 0.80 V, ID = 10 A ⇒ IS = 1.27× 10−13 A; ID × 10 gives V D = 0.86 V ID/10 gives VD = 0.74 V (d) VD = 0.70 V, ID = 1 mA ⇒ IS = 6.91× 10−16 A; ID × 10 gives V D = 0.76 V ID/10 gives VD = 0.64 V (e) VD = 0.6 V, ID = 10 μA ⇒ IS = 3.78× 10−16 A ID × 10 gives V D = 0.66 V ID/10 gives VD = 0.54 V 4.23 The voltage across three diodes in series is 2.0 V; thus the voltage across each diode must be 0.667 V. Using ID = ISeVD/VT , the required current I is found to be 3.9 mA. If 1 mA is drawn away from the circuit, ID will be 2.9 mA, which would give VD = 0.794 V, giving an output voltage of 1.98 V. The change in output voltage is −22 mV. 4.24 Connecting an identical diode in parallel would reduce the current in each diode by a factor of 2. Writing expressions for the currents, we have ID = ISeVD/VT ID 2 = ISe(VD−V)/VT = ISeVD/VT · e−V /V T Taking the ratio of the above two equations, we have 2 = eV /V T ⇒ V = 17.3 mV Thus the result is a decrease in the diode voltage by 17.3 mV. 4.25 VD   I ID2ID1 D1 D2 ID1 = IS1eVD/VT (1) ID2 = IS2eVD/VT (2) Summing (1) and (2) gives ID1 + ID2 = (IS1 + IS2)eVD/VT But ID1 + ID2 = I Thus I = (IS1 + IS2) eVD/VT (3) From Eq. (3) we obtain VD = VT ln ( I IS1 + IS2 ) Also, Eq. (3) can be written as I = IS1 eVD/VT ( 1+ IS2 IS1 ) (4) Now using (1) and (4) gives ID1 = I 1+ (IS2/IS1) = I IS1 IS1 + IS2 We similarly obtain ID2 = I 1+ (IS1/IS2) = I IS2 IS1 + IS2 4.26 I D2 D3 8I1 D4 4I12I1 I1  0.1 mA I1 D1 SEDRA-ISM: “P-CH04-014-030” — 2014/11/12 — 15:20 — PAGE 8 — #4 Chapter 4–8 The junction areas of the four diodes must be related by the same ratios as their currents, thus A4 = 2A3 = 4A2 = 8 A1 With I1 = 0.1 mA, I = 0.1+ 0.2+ 0.4+ 0.8 = 1.5 mA 4.27 We can write a node equation at the anodes: ID2 = I1 − I2 = 7 mA ID1 = I2 = 3 mA We can write the following equation for the diode voltages: V = VD2 − VD1 If D2 has saturation current IS , then D1, which is 10 times larger, has saturation current 10IS . Thus we can write ID2 = ISeVD2/VT ID1 = 10I SeVD1/VT Taking the ratio of the two equations above, we have ID2 ID1 = 7 3 = 1 10 e(VD2−VD1)/VT = 1 10 eV /V T ⇒ V = 0.025 ln ( 70 3 ) = 78.7 mV To instead achieve V = 60 mV, we need ID2 ID1 = I1 − I2 I2 = 1 10 e0.06/0.025 = 1.1 Solving the above equation with I1 still at 10 mA, we find I2 = 4.76 mA. 4.28 We can write the following node equation at the diode anodes: ID2 = 10 mA − V /R ID1 = V /R We can write the following equation for the diode voltages: V = VD2 − VD1 We can write the following diode equations: ID2 = ISeVD2/VT ID1 = ISeVD1/VT Taking the ratio of the two equations above, we have ID2 ID1 = 10 mA − V /R V /R = e(VD2−VD1)/VT = eV /V T To achieve V = 50 mV, we need ID2 ID1 = 10 mA − 0.05/R 0.05/R = e0.05/0.025 = 7.39 Solving the above equation, we have R = 42  4.29 For a diode conducting a constant current, the diode voltage decreases by approximately 2 mV per increase of 1◦C. T = −20◦C corresponds to a temperature decrease of 40◦C, which results in an increase of the diode voltage by 80 mV. Thus VD = 770 mV. T = + 85◦C corresponds to a temperature increase of 65◦C, which results in a decrease of the diode voltage by 130 mV. Thus VD = 560 mV. 4.30 D2 D1 R1 I 10 V V1   V2   At 20◦C: VR1 = V2 = 520 mV R1 = 520 k I = 520 mV 520 k = 1 μA Since the reverse current doubles for every 10◦C rise in temperature, at 40◦C, I = 4 μA V2 ID2 480 40°C 40 mV 20°C 520 mV 4 µA 1 µA V2 = 480+ 2.3× 1× 25 log 4 = 514.6 mV VR1 = 4 μA × 520 k = 2.08 V At 0◦C, I = 1 4 μA V2 = 560− 2.3× 1× 25 log 4 = 525.4 mV VR1 = 1 4 × 520 = 0.13 V SEDRA-ISM: “P-CH04-031-053” — 2014/11/12 — 17:25 — PAGE 11 — #3 Chapter 4–11 3. v = 0.7+ 2.3× 0.025 log ( 0.6255 1 ) = 0.6882 V 3 i = 1− 0.6882 0.5 k = 0.6235 mA 4. v = 0.7+ 2.3× 0.025 log ( 0.6235 1 ) = 0.6882 V 4 i = 1− 0.6882 0.5 k = 0.6235 mA Stop as we are getting the same result. 4.37 We first find the value of IS for the diode, given by IS = IDe−VD/VT with ID = 1 mA and VD = 0.75 V. This gives IS = 9.36× 10−17 A. In order to have 3.3 V across the 4 series-connected diodes, each diode drop must be 0.825 V. Applying this voltage to the diode gives current ID = 20.1 mA. We can then find the resistor value using R = 15 V − 3.3 V 20.1 mA = 582  4.38 Constant voltage drop model: Using vD = 0.7 V,⇒ iD1 = V − 0.7 R Using vD = 0.6 V,⇒ iD2 = V − 0.6 R For the difference in currents to be only 1%, ⇒ iD2 = 1.01iD1 V − 0.6 = 1.01 (V − 0.7) V = 10.7 V For V = 3 V and R = 1 k: At VD = 0.7 V, iD1 = 3− 0.7 1 = 2.3 mA At VD = 0.6 V, iD2 = 3− 0.6 1 = 2.4 mA iD2 iD1 = 2.4 2.3 = 1.04 Thus the percentage difference is 4%. 4.39 Available diodes have 0.7 V drop at 2 mA current since 2VD = 1.4 V is close to 1.3 V, use N parallel pairs of diodes to split the 1 mA current evenly, as shown in the figure next. N 1 mA   V The voltage drop across each pair of diodes is 1.3 V. ∴ Voltage drop across each diode = 1.3 2 = 0.65 V. Using I2 = I1e(V2−V1)/VT = 2e(0.65−0.7)/0.025 = 0.2707 mA Thus current through each branch is 0.2707 mA. The 1 mA will split in= 1 0.2707 = 3.69 branches. Choose N = 4. There are 4 pairs of diodes in parallel. ∴ We need 8 diodes. Current through each pair of diodes = 1 mA 4 = 0.25 mA ∴ Voltage across each pair = 2 [ 0.7+ 0.025 ln ( 0.25 2 )] = 1.296 V SPECIAL NOTE: There is another possible design utilizing only 6 diodes and realizing a voltage of 1.313 V. It consists of the series connection of 4 parallel diodes and 2 parallel diodes. 4.40 Refer to Example 4.2. (a) 10 k 5 k 10 V 1.861  0.86 mA 10 V V  0 V I   1.86 mA  1 mA  0.7 V 0.7  10 5 2 10  0 10 3 45 1 SEDRA-ISM: “P-CH04-031-053” — 2014/11/12 — 17:25 — PAGE 12 — #4 Chapter 4–12 (b) Cutoff 5 k 10 k ID2 10 V 10 V 0.7 V V I  0 ID2   ID2 = 10− (−10)− 0.7 15 = 1.29 mA VD = −10+ 1.29 (10)+ 0.7 = 3.6 V 4.41 (a) 10 k 3 V 3 V V I V = −3+ 0.7 = −2.3 V I = 3+ 2.3 10 = 0.53 mA (b) 10 k Cutoff 3 V 3 V V I I = 0 A V = 3− I (10) = 3 V (c) 10 k 3 V I 3 V V V = 3− 0.7 = 2.3 V I = 2.3+ 3 10 = 0.53 mA (d) 3 V 3 V Cutoff I V I = 0 A V = −3 V 4.42 (a) 2 k Cutoff 3 V 1 V 2 V I V D1 D2 V = 2− 0.7 = 1.3 V I = 1.3− (−3) 2 = 2.15 mA SEDRA-ISM: “P-CH04-031-053” — 2014/11/12 — 17:25 — PAGE 13 — #5 Chapter 4–13 (b) 2 k Cutoff 3 V I V1 V D1 D2 2 V V = 1+ 0.7 = 1.7 V I = 3− 1.7 2 = 0.65 mA 4.43 6 k + 3 V   3 V 0.7 V 12 k V I  0 ID2 ID2 D1 D2 Cutoff (a) ON 12 k  3 V  0.7 V 3 V 6 k (b) I  0.383  0.25 V  0 V D1 D2 ONON 6  0.383 mA  0.133 mA 30.7 12 0.25 mA 0(3)  (a) ID2 = 3− 0.7− (−3) 12+ 6 = 0.294 mA V = −3+ 0.294× 6 = −1.23 V Check that D1 is off: Voltage at the anode of D1 = V + VD2 = −1.23+ 0.7 = −0.53 V which keeps D1 off. (b) See analysis on Fig. (b). I = 0.133 mA V = 0 V 4.44 I 20 k 10  10  5 k 0.7 V 10 10  105 (a) V    2.5 V 1.5 V  V 5 k 5 k 2.5 V 0 mA (b) (a) I = 2.5− 0.7 5+ 20 = 0.072 mA V = 0.072× 20 = 1.44 V (b) The diode will be cut off, thus I = 0 V = 1.5− 2.5 = −1 V 4.45 vI iD R   iD,peak = v I ,peak − 0.7 R ≤ 40 mA R ≥ 120 √ 2− 0.7 40 = 4.23 k Reverse voltage = 120√2 = 169.7 V. The design is essentially the same since the supply voltage 0.7 V 4.46 Use the exponential diode model to find the percentage change in the current. iD = ISev/VT iD2 iD1 = e(V2−V1)/VT = ev/VT For +5 mV change we obtain SEDRA-ISM: “P-CH04-031-053” — 2014/11/12 — 17:25 — PAGE 16 — #8 Chapter 4–16 Equivalent Circuit rd rd rd rdvI vo R 10 k b. For signal current to be limited to ±10% of I (I is the biasing current), the change in diode voltage can be obtained from the equation iD I = eVD/V T = 0.9 to 1.1 vD = −2.63 mV to +2.32 mV  ±2.5 mV so the signal voltage across each diode is limited to 2.5 mV when the diode current remains within 10% of the dc bias current. ∴ vo = 10− 2.5− 2.5 = 5 mV and i = 5 mV 10 k = 0.5 μA vo R 10 k 2.5 mV 2.5 mV 2.5 mV 2.5 mV 10 mV i The current through each diode = 0.5 2 μA = 0.25 μA The signal current i is 0.5 μA, and this is 10% of the dc biasing current. ∴ DC biasing current I = 0.5× 10 = 5 μA c. Now I = 1 mA. ∴ ID = 0.5 mA Maximum current derivation 10%. ∴ id = 0.5 10 = 0.05 mA and i = 2id = 0.1 mA. ∴ Maximum vo = i × 10 k = 0.1× 10 = 1 V From the results of (a) above, for I = 1 mA, vo/v i = 0.995; thus the maximum input signal will be v̂ i = v̂o/0.995 = 1/0.995 = 1.005 V The same result can be obtained from the figure above where the signal across the two series diodes is 5 mV, thus v̂ i = v̂o + 5 mV = 1 V + 5 mV = 1.005 V. See also the figure below. 4.52 I v1 D1 i1 i3 i2 i4 D3 D2 iO vO D4 R 10 k v2 v4 v3         I vI I = 1 mA Each diode exhibits 0.7 V drop at 1 mA current. Using diode exponential model we have v2 − v1 = VT ln ( i2 i1 ) and v1 = 0.7 V, i1 = 1 mA ⇒ v = 0.7+ VT ln ( i 1 ) = 700+ 25 ln(i) SEDRA-ISM: “P-CH04-031-053” — 2014/11/12 — 17:25 — PAGE 17 — #9 Chapter 4–17 Calculation for different values of vO: vO = 0, iO = 0, and the current I = 1 mA divide equally between the D3, D4 side and the D1, D2 side. i1 = i2 = i3 = i4 = I 2 = 0.5 mA v = 700+ 25 ln(0.5)  683 mV v1 = v2 = v3 = v4 = 683 mV From the circuit, we have v I = −v1 + v3 + vO = −683+ 683+ 0 = 0 V For vO = 1 V, iO = 110 k = 0.1 mA Because of symmetry of the circuit, we obtain i3 = i2 = I 2 + iO 2 = 0.5+ 0.05 = 0.55 mA and i4 = i1 = 0.45 mA v3 = v2 = 700+ 25 ln ( i2 1 ) = 685 mV v4 = v1 = 700+ 25 ln ( i4 1 ) = 680 mV vO iO i3 = i2 i4 = i1 v3 = v2 v4 = v1 v I = −v1+ (V) (mA) (mA) (mA) (mV) (mV) v3 + vO (V) 0 0 0.5 0.5 683 683 0 + 1 0.1 0.55 0.45 685 680 1.005 + 2 0.2 0.6 0.4 ∼ 687 677 2.010 + 5 0.5 0.75 0.25 ∼ 693 665 5.028 + 9 0.9 0.95 0.05 ∼ 699 ∼ 625 9.074 + 9.9 0.99 0.995 0.005 ∼ 700 568 10.09 9.99 0.999 0.9995 0.0005 ∼ 700 510 10.18 10 1 1 0 700 0 10.7 v I = −v1 + v2 + vO = −0.680 +0.685+ 1 = 1.005 V Similarly, other values are calculated as shown in the table. The largest values of vO on positive and negative side are +10 V and −10 V, respectively. This restriction is imposed by the current I = 1 mA A similar table can be generated for the negative values. It is symmetrical. For v I > +10.7, vO will be saturated at +10 V and it is because I = 1 mA. Similarly, for v I < −10.7 V, vO will be saturated at −10 V. For I = 0.5 mA, the output will saturate at 0.5 mA×10 k = 5 V. vo (V ) v1 (V ) 10 5 5 5.68 5.6810.7 10.7 I  1 mA I  0.5 mA 4.53 Representing the diode by the small-signal resistances, the circuit is vi VT vo ID C    rd rd  Vo Vi = 1 sC rd + 1 sC = 1 1+ sCrd Vo Vi = 1 1+ jωCrd Phase shift = −tan−1 ( ωCrd 1 ) = −tan−1 ( ωC VT I ) For phase shift of −45◦, we obtain −45 = −tan−1 ( 2π × 100× 103 × 10 × 10−9 × 0.025 I ) ⇒ I = 157 μA Now I varies from 157 10 μA to 157× 10 μA Range is 15.7 μA to 1570 μA Range of phase shift is −84.3◦ to −5.71◦ SEDRA-ISM: “P-CH04-054-069” — 2014/11/12 — 15:21 — PAGE 18 — #1 Chapter 4–18 4.54 V VO R   (a) VO V+ = rd R+ rd = VT /I R+ VT I = VT IR+ VT For no load, I = V + − VO R = V + − 0.7 R . ∴ VO V+ = VT VT + (V+ − 0.7) Small-signal model   R V rd VO  (b) If m diodes are in series, we obtain VO V+ = mrd mrd + R = mVT mVT + IR = mVT mVT + (V+ − 0.7m) (c) For m = 1 VO V+ = VT VT + V+ − 0.7 = 1.75 mV/V For m = 4 VO V+ = mVT mVT + 15− m× 0.7 = 8.13 mV/V 4.55 R Small-signal model   IL IL rdR VO V VO (a) From the small-signal model VO = −IL (rd ‖ R) VO IL = − (rd ‖ R) (b) At no load, ID = V + − 0.7 R rd = VT ID VO IL = − (rd ‖ R) = − 11 rd + 1 R = − 1 ID V+ − 0.7 + ID VT = −VT ID × 1 VT V+ − 0.7 + 1 = −VT ID × V + − 0.7 VT + V+ − 0.7 For VO IL ≤ 5 mV mA i.e., VT ID × V + − 0.7 VT + V+ − 0.7 ≤ 5 mV mA[ 25 ID × 15− 0.7 0.025+ 15− 0.7 ] ≤ 5 mV mA ID ≥ 4.99 mA ID  5 mA R = V + − 0.7 ID = 15− 0.7 5 mA R = 2.86 k SEDRA-ISM: “P-CH04-054-069” — 2014/11/12 — 15:21 — PAGE 21 — #4 Chapter 4–21 I = 5− 1.4 0.2 = 18 mA ID = I = 18 mA Iteration #2: VD = 0.7+ 0.025 ln ( 18 10 ) = 0.715 V VO = 1.429 V I = 17.85 mA ID = 17.85 mA Iteration #3: VD = 0.7+ 0.025 ln ( 17.85 10 ) = 0.714 V VO = 1.43 V I = 17.86 mA ID = 17.86 mA No further iterations are warranted and VO = 1.43 V (c) VO = 1.39− 0.1 = 1.29 V IL = 1.29 0.15 = 8.6 mA VD = 1.29 2 = 0.645 V ID = 10× e(0.645−0.7)/0.025 = 1.11 mA I = IL + ID = 8.6+ 1.11 = 9.71 mA VSupply = VO + IR = 1.29+ 9.71× 0.2 = 3.232 V which is a reduction of 1.768 V or −35.4%. (d) For VSupply = 5+ 1.786 = 6.786 V, Iteration #1: VD = 0.7 V VO = 1.4 V IL = 9.33 mA I = 6.768− 1.4 0.2 = 26.84 ID = I − IL = 26.84− 9.33 = 17.51 mA Iteration #2: VD = 0.7+ 0.025 ln ( 17.51 10 ) = 0.714 V VO = 1.428 V IL = 9.52 mA I = 26.70 mA ID = 17.18 mA Iteration #3: VD = 0.7+ 0.025 ln ( 17.18 10 ) = 0.714 V VO = 1.428 V No further iterations are needed and VO = 1.43 V (e) From the above we see that as VSupply changes from 5 V to 3.232 V (a change of −35.4%) the output voltage changes from 1.39 V to 1.29 V (a change of −7.19%). As VSupply changes from 5 V to 6.786 V (a change of +35.4%) the output voltage changes from 1.39 V to 1.43 V (a change of +2.88%). Thus the worst-case situation occurs when VSupply is reduced, and Percentage change in VO per 1% change in VSupply = 7.19 35.4 = 0.2% 4.59 VZ = VZ0 + IZT rz (a) 10 = 9.6+ 0.05× rz ⇒ rz = 8  For IZ = 2IZT = 100 mA, VZ = 9.6+ 0.1× 8 = 10.4 V P = 10.4× 0.1 = 1.04 W (b) 9.1 = VZ0 + 0.01× 30 ⇒ VZ0 = 8.8 V At IZ = 2IZT = 20 mA, VZ = 8.8+ 0.02× 30 = 9.4 V P = 9.4× 20 = 188 mW (c) 6.8 = 6.6+ IZT × 2 ⇒ IZT = 0.1 A At IZ = 2IZT = 0.2 A, VZ = 6.6+ 0.2× 2 = 7 V P = 7× 0.2 = 1.4 W (d) 18 = 17.6+ 0.005× rz ⇒ rz = 80  SEDRA-ISM: “P-CH04-054-069” — 2014/11/12 — 15:21 — PAGE 22 — #5 Chapter 4–22 At IZ = 2IZT = 0.01 A, VZ = 17.6+ 0.01× 80 = 18.4 V P = 18.4× 0.01 = 0.184 W = 184 mW (e) 7.5 = VZ0 + 0.2× 1.5 ⇒ VZ0 = 7.2 V At IZ = 2IZT = 0.4 A, VZ = 7.2+ 0.4× 1.5 = 7.8 V P = 7.8× 0.4 = 3.12 W 4.60 (a) Three 6.8-V zeners provide 3× 6.8 = 20.4 V with 3 ×10 = 30- resistance. Neglecting R, we have Load regulation = −30 mV/mA. (b) For 5.1-V zeners we use 4 diodes to provide 20.4 V with 4 ×30 = 120- resistance. Load regulation = −120 mV/mA 4.61 Small-signal model   82  8  vOvS  From the small-signal model we obtain vO vS = 8 8+ 82 = 8 90 Now vS = 1.0 V. ∴ vO = 8 90 vS = 8 90 × 1.0 = 88.9 mV 4.62 VZ = VZ0 + IZT rZ 9.1 = VZ0 + 0.02× 10 ⇒ VZ0 = 8.9 V At IZ = 10 mA, VZ = 8.9+ 0.01× 10 = 9.0 V At IZ = 50 mA, VZ = 8.9+ 0.05× 10 = 9.4 V 4.63 IZ I 10 V VO  VZ (a) RL R IL I 11 V VZ0 rZ (b) R VO  VZ I 9 V VO  VZ (c) RL R IL0.5 mA SEDRA-ISM: “P-CH04-054-069” — 2014/11/12 — 15:21 — PAGE 23 — #6 Chapter 4–23 To obtain VO = 7.5 V, we must arrange for IZ = 10 mA (the current at which the zener is specified). Now, IL = VO RL = 7.5 1.5 = 5 mA Thus I = IZ + IL = 10+ 5 = 15 mA and R = 10− VO I = 10− 7.5 15 = 167  When the supply undergoes a change VS , the change in the output voltage, VO, can be determined from VO VS = (RL ‖ rz) (RL ‖ rz)+ R = 1.5 ‖ 0.03 (1.5 ‖ 0.03)+ 0.167 = 0.15 For VS = +1 V (10% high), VO = +0.15 V and VO = 7.65 V. For VS = −1 V (10% low), VO = −0.15 V and VO = 7.35 V. When the load is removed and VS = 11 V, we can use the zener model to determine VO. Refer to Fig. (b). To determine VZ0, we use VZ = VZ0 + IZT rz 7.5 = VZ0 + 0.01× 30 ⇒ VZ0 = 7.2 V From Fig. (b) we have I = 11− 7.2 0.167+ 0.03 = 19.3 mA Thus VO = VZ0 + Irz = 7.2+ 0.0193× 30 = 7.78 V To determine the smallest allowable value of RL while VS = 9 V, refer to Fig. (c). Note that IZ = 0.5 mA, thus VZ = VZK  VZ0 = 7.2 V I = 9− 7.2 0.167 = 10.69 mA IL = I − IZ = 10.69− 0.5 = 10.19 mA RL = VO IL = 7.2 10.19 = 707  VO = 7.2 V 4.64 9 V ± 1 V VO IZ R GIVEN PARAMETERS VZ = 6.8V, rz = 5  IZ = 20 mA At knee, IZK = 0.25 mA rz = 750  FIRST DESIGN: 9-V supply can easily supply current Let IZ = 20 mA, well above knee. ∴ R = 9− 6.8 20 = 110  Line regulation = VO VS = rZ rZ + R = 5 5+ 110 = 43.5 mV V SECOND DESIGN: limited current from 9-V supply IZ = 0.25 mA VZ = VZK  VZO − calculate VZ0 from VZ = VZ0 + rZ IZT 6.8 = VZ0 + 5× 0.02 VZ0 = 6.7 V ∴ R = 8− 6.7 0.25 = 5.2 k LINE REGULATION = VO VS = 750 750+ 5200 = 126 mV V SEDRA-ISM: “P-CH04-054-069” — 2014/11/12 — 15:21 — PAGE 26 — #9 Chapter 4–26 slope  1 0.7 V 0 vO vS (b) 0.7 V 0.7 V 10 V  10 V t vO vS u (c) The diode conducts at an angle θ = sin−1 ( 0.7 10 ) = 4◦ and stops at π − θ = 176◦ Thus the conduction angle is π − 2θ = 172◦ or 3 rad. vO,avg = −1 2π π−θ∫ θ (10 sin φ − 0.7) dφ = −1 2π [−10 cos φ − 0.7φ]π−θθ = −2.85 V (d) Peak current in diode is 10− 0.7 1 = 9.3 mA (e) PIV occurs when vS is at its the peak and vO = 0. PIV= 10 V 4.68 R     vS vO vD  D iD = ISevD/V T iD iD (1 mA) = e[vD−vD(at 1 mA)]/V T vD − vD(at 1 mA) = VT ln [ iD 1 mA ] vD = vD(at 1 mA)+ VT ln [ vO/R 1 ] vO = vS − vD = vS − vD (at 1 mA)− VT ln (vO R ) where R is in k. 4.69 R  1 k     vS vO 0.7 V 2.5 2.5 1.8 0.7 0 t t1 t2 TT 4 T 2 vS (V) First find t1 and t2 2.5 T 4 = 0.7 t1 ⇒ t1 = 0.07 T t2 = T 2 − t1 = T 2 − 0.07 T t2 = 0.43 T vO(ave.) = 1 T × area of shaded triangle = 1 T × (2.5− 0.7)× ( T 4 − t1 ) = 1 T × 1.8× T ( 1 4 − 0.07 ) = 0.324 V SEDRA-ISM: “P-CH04-070-085” — 2014/11/12 — 11:17 — PAGE 27 — #1 Chapter 4–27 4.70 1 k ideal 120 Vrms 60 Hz 0.7 V 12 : 1       vS vO10 Vrms v̂O = 10 √ 2− 0.7 = 13.44 V Conduction begins at 10 √ 2 sin θ = 0.7 θ = sin−1 ( 0.7 10 √ 2 ) = 2.84◦ = 0.0495 rad Conduction ends at π − θ . ∴ Conduction angle = π − 2θ = 3.04 rad The diode conducts for 3.04 2π × 100 = 48.4% of the cycle vO,avg = 1 2π π−θ∫ θ (10 √ 2sinφ − 0.7) dφ = 4.15 V iD,avg = vO,avg R = 4.15 mA 4.71 1 k10 Vrms 6 : 1 120 Vrms 60 Hz 10 Vrms     D2 D1 0  0.7 V 10 V t  vs vo vS , vO (V) vo v̂O = 10 √ 2− VD = 13.44 V Conduction starts at θ = sin−1 0.7 10 √ 2 = 2.84◦ = 0.05 rad and ends at π − θ . Conduction angle = π − 2θ = 3.04 rad in each half cycle. Thus the fraction of a cycle for which one of the two diodes conduct = 2(3.04) 2π × 100 = 96.8% Note that during 96.8% of the cycle there will be conduction. However, each of the two diodes conducts for only half the time, i.e., for 48.4% of the cycle. vO,avg = 1 π π−θ∫ θ (10 √ 2sinφ − 0.7)dφ = 8.3 V iL,avg = 8.3 1 k = 8.3 mA 4.72 1 k VD  0.7 V 120 Vrms 12 : 1 10 Vrms     D2 D1 D3 D4 R vs Peak voltage across R = 10√2− 2VD = 10√2− 1.4 = 12.74 V 1.4 V 10 2 V t  vS θ = sin−1 1.4 10 √ 2 = 5.68◦ = 0.1 rad Fraction of cycle that D1 & D2 conduct is π − 2θ 2π × 100 = 46.8% Note that D3 & D4 conduct in the other half cycle so that there is 2 (46.8) = 93.6% conduction interval. vO,avg = 2 2π π−θ∫ θ (10 √ 2sinφ − 2VD) dφ SEDRA-ISM: “P-CH04-070-085” — 2014/11/12 — 11:17 — PAGE 28 — #2 Chapter 4–28 = 1 π [ −12√2 cos φ − 1.4φ ]π−θ θ = 2(12 √ 2 cos θ) π − 1.4 (π − 2θ) π = 7.65 V iR,avg = vO,avg R = 7.65 1 = 7.65 mA 4.73 R       vS vS vO120 Vrms Refer to Fig. 4.24. For VD  Vs, conduction angle  π , and vO,avg = 2 π Vs − VD = 2 π Vs − 0.7 (a) For vO,avg = 10 V Vs = π 2 × 10.7 = 16.8 V Turns ratio = 120 √ 2 16.8 = 10.1 to 1 (b) For vO,avg = 100 V Vs = π 2 × 100.7 = 158.2 V Turns ratio = 120 √ 2 158.2 = 1.072 to 1 4.74 Refer to Fig. 4.25 For 2VD  Vs VO,avg = 2 π Vs − 2VD = 2 π Vs − 1.4 (a) For VO,avg = 10 V 10 V = 2 π · Vs − 1.4 ∴ V̂s = 11.4 (π 2 ) = 17.9 V Turns ratio = 120 √ 2 17.9 = 9.5 to 1 (b) For VO,avg = 100 V 100 V = 2 π · Vs − 1.4 ⇒ Vs = 101.4 (π 2 ) = 159 V Turns ratio = 120 √ 2 159 = 1.07 to 1 4.75 120 √ 2± 10%: 20√2± 10% ⇒ Turns ratio = 6:1 vS = 20 √ 2 2 ± 10% PIV= 2Vs − VD = 2× 20 √ 2 2 × 1.1− 0.7 = 30.4 V Using a factor of 1.5 for safety, we select a diode having a PIV rating of approximately 45 V. 4.76 The circuit is a full-wave rectifier with center tapped secondary winding. The circuit can be analyzed by looking at v+O and v − O separately. D1 D3     vS vS D4 R D2     vS vS vO vO, avg = 1 2π ∫ (VSsinφ − 0.7) dφ = 12 = 2Vs π − 0.7 = 12 where we have assumed Vs  0.7 V and thus the conduction angle (in each half cycle) is almost π . Vs = 12+ 0.7 2 π = 19.95 V SEDRA-ISM: “P-CH04-070-085” — 2014/11/12 — 11:17 — PAGE 31 — #5 Chapter 4–31 VpVD Vp Vp PIV t (c) When the diode is cut off, the maximum reverse voltage across it will occur when vS = −Vp. At this time, vO = VO and the maximum reverse voltage will be Maximum reverse voltage = VO + Vp = 12+ 13.7 = 25.7 V Using a factor of safety of 1.5 we obtain PIV = 1.5× 25.7 = 38.5 V (d) iDav = IL [ 1+ π √ 2(Vp − VD) Vr ] = VO RL [ 1+ π √ 2(Vp − VD) Vr ] = 12 0.2 [ 1+ π √ 2(13.7− 0.7) 2 ] = 739 mA (e) iDmax = IL [ 1+ 2π √ 2(Vp − VD) Vr ] = 12 0.2 [ 1+ 2π √ 2(13.7− 0.7) 2 ] = 1.42 A 4.81 0.7 V 0.7 V 120 Vrms 60 Hz RC   Vs   Vs   D1 D2 vO (a) VO = Vp − VD − 1 ⇒ Vp = VO + VD + 1 = 13+ 0.7 = 13.7 V Vrms = 13.7√ 2 = 9.7 V This voltage appears across each half of the transformer secondary. Across the entire secondary we have 2× 9.7 = 19.4 V (rms). PIV (b) Vr = Vp − VD 2fCR 2 = 13.7− 0.7 2× 60× 200× C ⇒ C = 12 2× 2× 60× 200 = 271 μF (c) Maximum reverse voltage across D1 occurs when vS = −Vp. At this point vO = VO. Thus maximum reverse voltage = VO + Vp = 12+ 13.7 = 25.7. The same applies to D2. In specifying the PIV for the diodes, one usually uses a factor of safety of about 1.5, PIV = 1.5× 25.7 = 38.5 V (d) iDav = IL [ 1+ π √ Vp − VD 2 Vr ] = 12 0.2 [ 1+ π √ 13.7− 0.7 2× 2 ] = 399 mA (e) iDmax = IL [ 1+ 2π √ Vp − VD 2 Vr ] = 12 0.2 [ 1+ 2π √ 13.7− 0.7 2× 2 ] = 739 mA 4.82 120 Vrms      vS vO D2 D1 D3 D4 R C 60 Hz (a) VO = Vp − 2VD − 1 ⇒ Vp = VO+2VD+1 = 12+2×0.7+1 = 14.4 V SEDRA-ISM: “P-CH04-070-085” — 2014/11/12 — 11:17 — PAGE 32 — #6 Chapter 4–32 Vrms = 14.4√ 2 = 10.2 V (b) Vr = Vp − 2 VD 2fCR ⇒ C = 14.4− 1.4 2× 2× 60× 200 = 271 μF (c) The maximum reverse voltage across D1 occurs when Vs = −Vp = −14.4 V. At this time D3 is conducting, thus Maximum reverse voltage = −Vp + VD3 = −14.4+ 0.7 = −13.7 V The same applies to the other three diodes. In specifying the PIV rating for the diode we use a factor of safety of 1.5 to obtain PIV = 1.5× 13.7 = 20.5 V (d) iDav = IL [ 1+ π √ Vp − 2 VD 2 Vr ] = 12 0.2 [ 1+ π √ 14.4− 1.4 2× 2 ] = 400 mA (e) iDmax = IL [ 1+ 2π √ Vp − 2 VD 2 Vr ] = 12 0.2 [ 1+ 2π √ 14.4− 0.7 2× 2 ] = 740 mA 4.83 (a) C R     100 F 100  vI vO vI Vr vO 12 V 12 V 11.3 V t vI  (b) T 1 ms Vr Vr 12 V 11.3 11.3   10.2 V  1.13 V 0 t } T 4 (c) During the diode’s off interval (which is almost equal to T ) the capacitor discharges and its voltage is given by vO(t) = 11.3 e−t/CR where C = 100 μF and R = 100 , thus CR = 100× 10−6 × 100 = 0.01 s At the end of the discharge interval, t  T and vO = 11.3 e−T/CR Since T = 0.001 s is much smaller than CR, vO  11.3 ( 1− T CR ) The ripple voltage Vr can be found as Vr = 11.3− 11.3 ( 1− T CR ) = 11.3T CR = 11.3× 0.001 0.01 = 1.13 V The average dc output voltage is vO = 11.3− Vr 2 = 11.3− 1.13 2 = 10.74 V To obtain the interval during which the diode conducts, t, refer to Fig. (c). 12 T /4 = Vr t ⇒ t = Vr × (T/4) 12 = 1.13× 1 12× 4 = 23.5 μs Now, using the fact that the charge gained by the capacitor when the diode is conducting is equal to the charge lost by the capacitor during its discharge interval, we can write iCav × t = C Vr ⇒ iCav = C Vr t = 100× 10−6 × 1.13 23.5× 10−6 = 4.8 A iDav = iCav + iLav where iLav is the average current through R during the short interval t. This is approximately 11.3 R = 11.3 100 = 0.113 A. Thus SEDRA-ISM: “P-CH04-070-085” — 2014/11/12 — 11:17 — PAGE 33 — #7 Chapter 4–33 iDav = 4.8+ 0.113 = 4.913 A Finally, to obtain the peak diode current, we use iDmax = iCmax + iLmax = C dv I dt + 11.3 R = C × 12 T/4 + 11.3 R = 100× 10−6 × 12× 4 1× 10−3 + 11.3 100 = 4.8+ 0.113 = 4.913 A which is equal to the average value. This is a result of the linear v I which gives rise to a constant capacitor current during the diode conduction interval. Thus iCmax = iCav = 4.8 A. Also, the maximum value of iL is approximately equal to its average value during the short interval t. 4.84 Refer to Fig. P4.76 and let a capacitor C be connected across each of the load resistors R. The two supplies v+O and v − O are identical. Each is a full-wave rectifier similar to that of the tapped-transformer circuit. For each supply, VO = 12 V Vr = 1 V (peak to peak) Thus vO = 12± 0.5 V It follows that the peak value of vS must be 12.5+ 0.7 = 13.2 V and the total rms voltage across the secondary will be = 2× 13.2√ 2 = 18.7 V (rms) Transformer turns ratio = 120 18.7 = 6.43:1 To deliver 100-mA dc current to each load, R = 12 0.1 = 120  Now, the value of C can be found from Vr = Vp − 0.7 2fCR 1 = 12.5 2× 60× C × 120 ⇒ C = 868 μF To specify the diodes, we determine iDav and iDmax, iDav = IL(1+ π √ (Vp − 0.7)/2 Vr ) = 0.1(1+ π√12.5/2 ) = 785 mA iDmax = IL(1+ 2π √ (Vp − 0.7)/2 Vr ) = 0.1(1+ 2π√12.5/2 ) = 1.671 A To determine the required PIV rating of each diode, we determine the maximum reverse voltage that appears across one of the diodes, say D1. This occurs when vS is at its maximum negative value −Vp. Since the cathode of D1 will be at +12.5 V, the maximum reverse voltage across D1 will be 12.5+ 13.2 = 25.7 V. Using a factor of safety of 1.5, then each of the four diodes must have PIV = 1.5× 25.7 = 38.6 V 4.85 Refer to Fig. P4.85. When v I is positive, vA goes positive, turning on the diode and closing the negative feedback loop around the op amp. The result is that v− = v I , vO = 2v− = 2v I , and vA = vO + 0.7. Thus (a) v I = +1 V, v− = +1 V, vO = +2 V, and vA = +2.7 V. (b) v I = +3 V, v− = +3 V, vO = +6 V, and vA = +6.7 V. When v I goes negative, vA follows, the diode turns off, and the feedback loop is opened. The op amp saturates with vA = −13 V, v− = 0 V and vO = 0 V. Thus (c) v I = −1 V, v− = 0 V, vO = 0 V, and vA = −13 V. (d) v I = −3 V, v− = 0 V, vO = 0 V, and vA = −13 V. Finally, if v I is a symmetrical square wave of 1-kHz frequency, 5-V amplitude, and zero average, the output will be zero during the negative half cycles of the input and will equal twice the input during the positive half cycles. See figure. vO vI 10 V 5 V 5 V 1 ms t 0 Thus, vO is a square wave with 0-V and +10-V levels, i.e. 5-V average and, of course, the same frequency (1 kHz) as the input. SEDRA-ISM: “P-CH04-086-097” — 2014/11/12 — 16:26 — PAGE 36 — #3 Chapter 4–36 This figure belongs to Problem 4.88, part b. 3.7 3.50 3.5 3.5 (Not to scale) slope  1 3.7 4.2 4.2 3.5 vO (V) vI (V) D1 OFF D2 ON D1 and D2 OFF (b) D1 ON D2 OFF Figure (b) shows a sketch of the transfer characteristic of this double limiter. 4.89 See figure. vI vO 3 V D1 D2 (a) R  0.5 k vI (V) vO (V) 3.7 3.5 2.5 (Not to scale) (b) slope  1 2.3 1.8 D1 ON D2 OFF D1 & D2 OFF D1 OFF D2 ON 2.5 3.5 4.2 4.90 D4 D1 D2 D3 1 k Z (a) vI vO The limiter thresholds and the output saturation levels are found as 2× 0.7+ 6.8 = 8.2 V. The transfer characteristic is given in Fig. (b). See figure on next page. 4.91 vI vO D2 1 k D1 SEDRA-ISM: “P-CH04-086-097” — 2014/11/12 — 16:26 — PAGE 37 — #4 Chapter 4–37 This figure belong to Problem 4.90, part b. Z Z All diodes and zener are OFF Diodes have 0.7 V drop at 1 mA current ∴ For diode D1 iD 1 mA = e(vO−0.7)/VT iD = 1× 10−3 e(vO−0.7)/VT vO = 0.7+ VT ln ( iD 1 mA ) v I = vO + iD × 1 k Using these equations, calculate v I for the different values of vO. For D2, v I = vO − iD × 1 k vO (V) vI (V) 112 2 0.8 to 55.4 0.8 It is a soft limiter with a gain K  1 and L+  0.7 V, L−  −0.7 V 4.92 (a)  vO    10 k vI SEDRA-ISM: “P-CH04-086-097” — 2014/11/12 — 16:26 — PAGE 38 — #5 Chapter 4–38 (b)  vOvI    10 k (c)  vOvI    10 k 4.93 vI   1.5 V 1.5 V vO   R 1 k In the nonlimiting region vO v I = 1000 1000+ R ≥ 0.94 R ≤ 63.8  4.94 VA I VB VC D3 5 k 1 k D1 I1 D4D2 I2 Figure 1 When VA > 0, D1 and D2 are cut off and D3 and D4 conduct a current I2. Since the diodes are 0.1-mA devices, the current I2 is related to the diode voltage VD as follows: I2 = 0.1× e(VD − 0.7)/0.025, mA (1) The voltage VC is given by VC = I2 × 1 k = I2, V (2) where I2 is in mA, and the voltage VB is given by VB = 2VD + VC (3) and the voltage VA is given by VA = VB + I × 5k VA = VB + 5I2 (4) Equations (1), (2), (3), and (4) can be used to find VB and VC versus VA. We start with a value for VD, use (1) to determine I2, use (2) to determine VC , use (3) to determine VB, and finally use (4) to determine VA. The results are given in Table 1. Table 1 VD3, VD4 I2 (mA) VC (V) VB = VC VA (V) (V) +VD3+ VD4 0.4  0 0 0.8 0.8 0.5 0.00003  0 1.0 1.0 0.6 0.002 0.002 1.202 1.212 0.7 0.1 0.1 1.5 2.0 0.73 0.332 0.332 1.792 3.452 0.735 0.406 0.406 1.876 3.91 0.74 0.495 0.495 1.975 4.45 0.745 0.605 0.605 2.095 5.12 For VA < 0, D3 and D4 are cutoff, I2 = 0, VC = 0, and D1 and D2 are conducting a current I1, I1 = 0.1 e(VD−0.7)/0.025, mA (5) The voltage VB is given by VB = −2VD (6) and the voltage VA is VA = VB − 5I1 (7) Equations (5)–(7) can be used to obtain VB versus VA for negative values of VA. The results are given in Table 2. Table 2 VD1, VD2 I 1 VB (V) VA (V) (mA) (V) 0.4  0 – 0.8 – 0.8 0.5  0 –1.0 –1.0 0.6 0.002 –1.2 –1.21 0.7 0.1 –1.4 –1.9 0.73 0.332 –1.46 –3.12 0.74 0.495 –1.48 –3.955 0.75 0.739 –1.5 –5.20