Chapter 8-SPICE for Power Electronics and Electric Power-Book, Lecture notes of Power Electronics

Download Chapter 8-SPICE for Power Electronics and Electric Power-Book and more Lecture notes Power Electronics in PDF only on Docsity! 242 SPICE for Power Electronics and Electric Power, Second Edition SOLUTION The DC supply voltage VS = 220 V, k = 0.5, fo = 1 kHz, T = 1/fo = 1 msec, and ton = k × T = 0.5 × 1 msec = 0.5 msec. angular signal Vref with a carrier signal Vcr generates a PWM waveform. The PWM generator is implemented as a descending hierarchy as shown in Figure 8.3(b). An ABM2 device that compares the two signals produces a square wave output V_Duty_Cycle can vary the duty cycle of the switch and the average output voltage. The model parameters for the switch and the freewheeling diode are as follows: .MODEL SMD VSWITCH (RON=1M ROFF=10E6 VON=1V VOFF=0V) .MODEL DMD D(IS=2.22E-15 BV=1200V CJO=1PF TT=0US)) FIGURE 8.1 DC switch chopper. (a) Circuit, (b) output voltage and current. FIGURE 8.2 DC chopper for PSpice simulation. (a) Circuit, (b) gate voltage. • • • • + + − − Vs vo io vo vs io l2 l1 R L S1 Dm 0 kT T t 0 kT T t (b) Output voltage and current(a) Circuit • • • • •••• • 1 3 Vs = 220 V, DC 0 6 + + − + − − Dm R L vo Vx iDm io vg vg tw tr = tf = 1 ns td = 0 tw = 0.5 msRg 10 MΩ 5 Ω S1 Vy 0 V 0 V 0 0.5 1 t (ms) 10 V 7.5 MH 5 4 (a) Circuit (b) Gate voltage DC–DC Converters 243 The list of the circuit file is as follows: FIGURE 8.3 PSpice schematic for Example 8.1. (a) Schematic, (b) descending hierarchy comparator. EXAMPLE 8.1 Chopper circuit SOURCE
VS 1 0 DC 220V Vg 6 0 PULSE (0V 10V 0 1NS 1NS 0.5MS 1MS) Rg 6 0 10MEG CIRCUIT

R 3 4 5 L 4 5 7.5MH VX 5 0 DC 0V ; Load battery voltage VY 2 3 DC 0V ; Voltage source to measure chopper current DM 0 3 DMOD ; Freewheeling diode .MODEL DMOD D(IS=2.22E−15 BV=1200V CJO=0PF TT=0) ; Diode model S1 1 2 6 0 SMOD ; Switch .MODEL SMOD VSWITCH (RON=1M ROFF=10E+6 VON=1V VOFF=0V) 4 I Vx 0 V + − 5 V 0 Vs 220 + − is PWM_Triangular Vcr Vg fer V 0.50 + − io 3 + − + − SMD S1 Vy 0 V + − 2 I 1 R 5 Vref FS = 1 kHz +− L 7.5 mH DMD Dm V_Duty_Cycle (a) Vg Vref IF (V(%IN1) − V(%IN2) > 0, 1, 0) Vcr (b) 246 SPICE for Power Electronics and Electric Power, Second Edition The area factor is used to determine the number of equivalent parallel BJTs of the model specified. The model parameters, which are affected by the area as an intrinsic transistor with ohmic resistances in series with the collector (RC/area), the base (RB/area), and the emitter (RE/area). [(area) value] is the relative device area, defaults to 1. For those parameters that have alternative FIGURE 8.5 PSpice BJT model. (a) Gummel and Poon model, (b) DC model, (C) Ebers–Moll model. • • •• • • • • • • •• • • • • • • • • • •• • •• C C S Substrate Rc Rc RE RE E E Emitter Ccs (Ibe1 − Ibc1)/Kqb (Ibe1 − Ibc1)/Kqb Collector Ibc1/βRIbc2 CjcCjc RBB RB B RB B Base Cje Ibe2 Ibc2 Ibe2 Cbc Rc Ic C IE RE E Cbe Ibe1/βF Ibc1/βR αF/IE αR/Ic Ibe1/βF (a) Gummel and poon model (b) Dc model (c) Ebers-Moll model DC–DC Converters 247 TABLE 8.1 Model Parameters of BJTS Name Area Model Parameter Unit Default Typical IS * p-n Saturation current A 1E−16 1E−16 BF Ideal maximum forward beta 100 100 NF Forward current emission coefficient 1 1 VAF(VA) Forward Early voltage V • 100 IKF(IK) Corner for forward beta high-current roll-off A • 10M ISE(C2) Base–emitter leakage saturation current A 0 1000 NE Base–emitter leakage emission coefficient 1.5 2 BR Ideal maximum reverse beta 1 0.1 NR Reverse current emission coefficient 1 VAR(VB) Reverse Early voltage V • 100 IKR * Corner for reverse beta high-current roll-off A • 100M ISC(C4) Base–collector leakage saturation current A 0 1 NC Base–collector leakage emission coefficient 2 2 RB * Zero-bias (maximum) base resistance W 0 100 RBM Minimum base resistance W RB 100 IRB Current at which RB falls halfway to RBM A • RE * Emitter ohmic resistance W 0 1 RC * Collector ohmic resistance W 0 10 CJE * Base–emitter zero-bias p-n capacitance F 0 2P VJE(PE) Base–emitter built-in potential V 0.75 0.7 MJE(ME) Base–emitter p-n grading factor 0.33 0.33 CJC * Base–collector zero-bias p-n capacitance F 0 1P VJC(PC) Base–collector built-in potential V 0.75 0.5 MJC(MC) Base–collector p-n grading factor 0.33 0.33 XCJC Fraction of Cbc connected internal to Rb 1 CJS(CCS) Collector–substrate zero-bias p-n capacitance F 0 2PF VJS(PS) Collector–substrate built-in potential V 0.75 MJS(MS) Collector–substrate p-n grading factor 0 FC Forward-bias depletion capacitor coefficient 0.5 TF Ideal forward transit time sec 0 0.1NS XTF Transit-time bias dependence coefficient 0 VTF Transit-time dependency on Vbc V • ITF Transit-time dependency on Ic A 0 PTF Excess phase at 1/(2π × TF)Hz degree 0 30° TR Ideal reverse transit time sec 0 10NS EG Band-gap voltage (barrier height) eV 1.11 1.11 XTB Forward and reverse beta temperature coefficient 0 XTI(PT) IS temperature effect exponent 3 KF Flicker noise coefficient 0 6.6E−16 AF Flicker noise exponent 1 1 248 SPICE for Power Electronics and Electric Power, Second Edition names such as VAF and VA (the alternative name is indicated is parentheses), either name may be used. The parameters ISE (C2) and ISC (C4) may be set to be greater than 1. In this case they are interpreted as multipliers of IS instead of absolute currents: that is, if ISE > 1, it is replaced by ISE*IS, and similarly for ISC. The DC model is defined by (1) parameters BF, C2, IK, and NE, which determine the forward current gain, (2) BR, C4, IKR, and VC, which determine the reverse current gain characteristics, (3) VA and VB, which determine the output conductance for forward and reverse regions, and (4) the reverse saturation current IS. Base-charge storage is modeled by (1) forward and reverse transit times TF and TR, and nonlinear depletion-layer capacitances, which are determined by CJE, PE, and ME for a base–emitter junction, and (2) CJC, PC, and MC for a base–collector junction. CCS is a constant collector–substrate capacitance. The temperature dependence of the saturation current is determined by the energy gap EG and the saturation current temperature exponent PT. The parameters that affect the switching behavior of a BJT are the most important ones for power electronics applications: IS, BF, CJE, CJC, and TF. The symbol of a bipolar junction transistor (BJT) is Q. The name of a bipolar transistor must start with Q and it takes the general form Q<name> NC NB NE NS QNAME [(area) value] where NC, NB, NE, and NS are the collector, base, emitter, and substrate nodes, respectively. QNAME could be any name of up to eight characters. The substrate node is optional: If not specified, it defaults to ground. Positive current is the current that flows into a terminal. That is, the current flows from the collector node, through the device, to the emitter node for an NPN BJT. 8.4 BJT PARAMETERS parameters are not available from the data sheet. Some versions of SPICE (e.g., PSpice) support device library files. The software PARTS of PSpice can generate SPICE models from the data sheet parameters of transistors and diodes. Although PSpice allows one to specify many parameters, we shall use only those parameters that affect significantly the output of a power converter [8,9]. From the data sheet we get Assuming that n = 1 and VT = 25.8 mV, we can apply Equation 7.1 to find the saturation current Is: I V I C(rated) BE C 10 A V at A = = =0 8 2. DC–DC Converters 251 where m = and V0 = 0.75 V. From Equation 8.2, Cµo = CJC = 607.3 pF at VCB = 10 V. The transition frequency fT(min) = 6 MHz at VCE = 10 V, IC = 500 mA. The transition period is τT = 1/2πfT = 1/(2π × 6 MHz) = 26,525.8 psec. Thus VCB ≈ VCE − VBE = 10 − 0.7 = 9.3 V, and Equation 8.2 gives Cµ = 255.7 pF. The transconductance gm is FIGURE 8.6 (continued). TYPICAL ELECTRICAL CHARACTERISTICS Figure 1–DC current gain Figure 3–“ON” Voltage Figure 5–Turn-on time Figure 6–Turn-off time Figure 4–Temperature coefficients Figure 2–Collector saturation region 100 2.0 1.6 1.2 0.8 0.4 0 2.5 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 −2.5 10 k 7.0 k 5.0 k 3.0 k 2.0 k 1.0 k 700 500 300 200 100 70 50 30 20 10 7.0 5.0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 3.0 k 2.0 k 1.0 k 700 500 300 200 100 70 50 30 0 0.2 0.3 0.5 1.0 2.0 3.0 5.0 7.0 10 20 0.2 0.02 0.5 0.1 0.2 0.5 1.0 2.0 5.0 10 20 0.3 0.5 1.0 2.0 3.0 5.0 7.0 10 20 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 IC, Collector current (amp) IC, Collector current (amp) IC, Collector current (amp) 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 IC, Collector current (amp) 0.2 0.3 0.5 1.0 2.0 3.0 5.0 7.0 10 20 IC, Collector current (amp) IC, Collector current (amp) h F E , D C c u rr en t g ai n V , V o lt ag e (v o lt s) t, T im e (n s) t, T im e (n s) V C E , C o ll ec to r em it te r (v o lt s) TJ = 150°C 25°C −55°C VCE = 2.0 V VCE = 10 V VCC = 250 V IC/IB = 5.0 TJ = 25°C VCC = 250 V IB1 = IB2 IC/IB = 5.0 TJ = 25°C TJ = 25°C IC = 2.0 A 15 A10 A5.0 A TJ = 25°C VBE(sat) @ IC/IB = 5.0 VCE(sat) @ IC/IB = 5 td @ VBE(off) = 5.0 V VBE(on) @ VCE = 2.0 V *Applies for IC/IB ≤ hFE/3 *θVC forVCE(sat) θVB forVBE 25°C to 150°C −55°C to 25°C 25°C to 150°C −55°C to 25°Cθ V , T em p er at u re c o effi ci en ts (m V /° C ) tr ts tf 1 3 252 SPICE for Power Electronics and Electric Power, Second Edition (8.3) The transition period τT is related to forward transit time τF by FIGURE 8.6 (continued). Figure 7–Forward operating area Figure 9–Power derating Figure 10–Thermal response Figure 8–Reverse bias safe operating area 50 20 16 12 8.0 4.0 0 20 10 5.0 1.0 0.5 0.005 100 80 60 40 20 0 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 5.0 0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 10 k 40 80 120 160 200 7.0 10 20 30 50 70 100 200 300 400 0 100 200 300 400 500 0.01 0.02 0.05 0.1 0.2 2.0 10 ns 1.0 ms5.0 ms 100 µs dc Bonding wire limit Thermal limit (single pulse) Second breakdown limit Curves apply below rated VCEO VCE, Collector-emitter voltage (volts) TC, Case temperature (°C) P o w er d er at in g f ac to r (% ) VCE, Collector-emitter voltage (volts) I C , C o ll ec to r cu rr en t (a m p ) I C , C o ll ec to r cu rr en t (a m p ) 2N6546 2N6547 Turn off load line boundary for 2N6547 for 2N6546. VCEO and VCEX are 100 volts less. VCEX(sus) VBE(off) < 5 V TC < 100°C VCEO(sus) VCEX(sus) 8.0 A TC = 25°C Second breakdown derating Thermal derating P(pk) ZθJC(t) = r(t)RθJC RθJC = 1.0°C/W Max D curves apply for power pulse train shown read time at t1 Duty cycle D = t1·t2 t1 t2 TJ(pk) − ΤC = P(pk) ZθJC(t) r( t) , T ra n si en t th er m al re si st an ce ( n o rm al iz ed ) D = 0.5 0.2 0.1 0.05 0.02 0.01 Single pulse t, Time (ms) There are two limitations on the power handling ability of a transistor: Average junction temperature and second breakdown. Safe operating area curves indicate IC−VCE limits of the transistor that must not be subjected to greater dissipation than the curves indicate. The data of figure 7 is based on TC = 25°C; TJ(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC ≥ 25°C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on figure 7 may be found at any case temperature by using the appropriate curve on figure 9. TJ(pk) may be calculated from the data in figure 10. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdwon. g I V C T m mA 25.8 mV A/V = = =500 19 38. DC–DC Converters 253 or (8.4) which gives τF = 26,512.6 psec. Thus, the PSpice model statement for transistor 2N6546 is .MODEL 2N6546 NPN (IS=6.83E−14 BF=13 CJE=1 PF CJC=607.3PF TF=26.5NS) This model can be used to plot the characteristics of the MOSFET. It may be necessary to modify the parameter values to conform to the actual characteristics. Note: It is often necessary to adjust the base resistance RB or base (control) voltage Vg so that the transistor is driven into saturation. 8.5 EXAMPLES OF BJT CHOPPERS The applications of the SPICE BJT model are illustrated by some examples. EXAMPLE 8.2 FINDING THE PERFORMANCE OF A STEP-DOWN DC–DC CONVERTER WITH A BJT SWITCH S The load resistance R is 5 Ω. The filter inductance is L = 145.84 µH, and the filter capacitance is C = 200 µF. The chopping frequency is fc = 25 kHz, and the duty cycle of the chopper is k = 42%. The control voltage is shown in Figure 8.7(b). Use PSpice to(a) plot the instantaneous load current io, the input current is, the diode voltage vD, and the output voltage vC and (b) calculate the Fourier coefficients of the input current is. Plot the frequency response of the converter output voltage from 10 kHz to 10 MHz and find the resonant frequency. SOLUTION S c c ton = k × T = 16.7 µsec. An initial value for C is assigned to reach steady state faster. with a gain of 30 drives the BJT switch. The PWM generator is implemented as a switch and the freewheeling diode are as follows: .MODEL QMOD NPN(IS=6.83E-14 BF=13 CJE=1pF CJC=607.3PF TF=26.5NS) .MODEL DMD D(IS=2.22E-15 BV=1200V CJO=1PF TT=0US)) τ τ τ T F je m m Fpsec pF = + + = + + C g C g
26 525 8 1 19 38 25 , . . 5 7 19 38 . . pF 256 SPICE for Power Electronics and Electric Power, Second Edition res = 872.15 Hz at a resonant peak gain of Ao(peak) = 3.16. Note: The base resistance RB is needed to limit the base drive current of the BJT switch. The LC output filter is needed to reduce the ripples on the load voltage and current. For a duty cycle of k = 0.42, the average voltage at the output of the converter [1] is Vo(av) = kVs = 0.42 × 12 = 5.04 V. EXAMPLE 8.3 FINDING THE PERFORMANCE OF A BUCK–BOOST DC–DC CONVERTER WITH A BJT SWITCH s = 12 V. The load resistance R is 5 Ω. The inductance is L = 150 µH, and the filter capacitance is C = 200 µF. The chopping frequency is fc = 25 kHz, and the duty cycle of the chopper is k = 25%. The control voltage is shown in Figure 8.10(b). Use PSpice to plot the instantaneous output voltage vc, the capacitor current ic, the inductor current iL, and the inductor voltage vL. Plot the frequency response of the converter output voltage from 100 kHz to 10 MHz and find the resonant frequency. SOLUTION The DC supply voltage VS = 12 V, k = 0.25, fc = 25 kHz, T = 1/fc = 40 µsec, and ton = k × T = 0.25 × 40 = 10 µsec. with a gain of 40 drives the BJT switch. The PWM generator is implemented as a switch and the freewheeling diode are as follows: .MODEL QMOD NPN(IS=6.83E-14 BF=13 CJE=1pF CJC=607.3PF TF=26.5NS) .MODEL DMD D(IS=2.22E-15 BV=1200V CJO=1PF TT=0US)) The list of the circuit file is as follows: DC–DC Converters 257 res = 872.15 Hz at a resonant peak gain of Ao(peak) = 3.2. the switch voltage and the converter output voltage. The output voltage is negative. For a duty cycle of k = 0.25, the average load voltage is Vo(av) = kVs /(1 − k) = 0.25 × 12/(1 − 0.25) = 4V (PSpice gives 3.5 V). The load voltage has not yet reached the steady-state value. .MODEL DMOD D(IS=2.22E−15 BV=1200V IBV=13E−3 CJO=0 TT=0) ; Diode model Q1 2 6 3 3 2N6546 ; BJT switch .MODEL 2N6546 NPN (IS=6.83E−14 BF=13 CJE=1PF CJC=607.3PF TF=26.5NS) ANALYSIS


.TRAN 0.1US 1MS 750US UIC ; Transient analysis .PROBE ; Graphics post-processor .OPTIONS ABSTOL = 1.00N RELTOL = 0.01 VNTOL = 0.1 ITL5 = 40000 .FOUR 25KHZ I(VY) ;Fourier analysis .END FIGURE 8.9 Plots for Example 8.2. (a) Transient plots, (b) Frequency response. Time 2.00 ms 2.02 ms 2.04 ms 2.06 ms 2.08 ms 2.10 ms V(4) 2.0 V 3.0 V 4.0 V 5.0 V V(3) 5 V 10 V 15 V I(VY) 0 A 0.5 A 1.0 A 1.5 A I(L) 0 A 1.0 A 1.5 A SEL>> Inductor current (2.0568 m, 1.2772) Input current Converter output voltage Load voltage (2.0577 m, 4.3486) (a) 258 SPICE for Power Electronics and Electric Power, Second Edition FIGURE 8.9 (continued). FIGURE 8.10 BJT buck–boost chopper for PSpice simulation. (a) Circuit, (b) control voltage. Frequency 10 KHz 100 KHz 1.0 MHz 10 MHz VP(3) 0 d 90 d 180 d Phase V(3) 0 V 2.0 V 3.0 V 4.0 V SEL>> Magnitude (872.156 K, 3.1680) (b) • • • • • • • • • •• + + + 1 0 2 7 12 V, dc 3 4 5 0 V 3 V R 6 250 Ω 5 Ω150 µF Vy Vs RB VL L 220 µF C iL ic iovg Q1 Vx Dm − − − − − vc + + vg 0 10 40 t (µs) (a) Circuit (b) Control voltage 40 V DC–DC Converters 261 .MODEL QMOD NPN(IS=6.83E-14 BF=13 CJE=1pF CJC=607.3PF TF=26.5NS) .MODEL DMD D(IS=2.22E-15 BV=1200V CJO=1PF TT=0US)) SOLUTION The DC supply voltage VS = 12 V. An initial capacitor voltage VC = 3 V, k = 0.25, fc = 25 kHz, T = 1/fc = 40 µsec, and ton = k × T = 0.25 × 40 = 10 µsec. The list of the circuit file is as follows: FIGURE 8.14 PSpice schematic for Example 8.4. Example 8.4 BJT cuk chopper SOURCE
VS 1 0 DC 12V VY 1 2 DC 0V ; Voltage source to measure input current Vg 8 0 PULSE (0V 40V 0 0.1NS 0.1NS 10US 40US) CIRCUIT

RB 8 7 25 ; Transistor base resistance R 6 0 5 L1 2 3 200UH C1 3 4 200UF L2 5 6 150UF C2 6 0 220UF IC=0V ; Initial conditions VX 4 5 DC ; Voltage source to measure current of L2 DM 4 0 DMOD .MODEL DMOD D(IS=2.22E−15 BV=1200V IBV=13E−3 CJO=0 TT=0) ; Diode model Q1 3 7 0 2N6546 ; BJT switch .MODEL 2N6546 NPN (IS=6.83E−14 BF=13 CJE=1PF CJC=607.3PF TF=26.5NS) PWM_Triangular Vcr Vg V re f I RB 250 1 I is DMD Dm 2Vy 0 V + - 4 I V R 5 L1 200 uH io C2 220 uF 5 Vref FS = 25 kHz+- Vx 0 V + - 6 C1 200 uF L2 150 uH 7 Vs AC = 1 V DC = 12 V + - 0.25 + - 8-+ + - E1 Gain 40 3 4 QMOD Q1 V_Duty_Cycle 262 SPICE for Power Electronics and Electric Power, Second Edition The PSpice plots of the instantaneous capacitor current I(C1), the capacitor current I(C2), the inductor current I(L1), the inductor current I(L2), and the transistor state. Figure 8.15(b) gives the resonant frequency of fres =833.28 Hz at a resonant peak gain of Ao(peak) = 6.8. Note: The base drive voltage is increased to 40 V in order to reduce distortion on the switch voltage and the converter output voltage. The output voltage is negative. For a duty cycle of k = 0.25, the average load voltage is Vo(av) = kVs/(1−k) = 0.25 × 12/(1−0.25) = 4 V (PSpice gives 3.5 V). The load voltage has not yet reached the steady-state value. If we run the simulation for a longer time as shown in Figure 8.15, we can find out the oscillation of the converter output voltage at its natural frequency. 8.6 MOSFET CHOPPERS The static (DC) model that is generated by PSpice is shown in Figure 8.17(b). The model parameters for a MOSFET device and the default values assigned by by PSpice are described in Reference 4 and Reference 6. The model statement of n-channel MOSFETs has the general form .MODEL MNAME NMOS (P1=V1 P2=V2 P3=V3 … PN=VN) and the statement for p-channel MOSFETs has the form .MODEL MNAME PMOS (P1=V1 P2=V2 P3=V3 … PN=VN) where MNAME is the model name. It can begin with any character, and its word size is normally limited to eight characters. NMOS and PMOS are the type symbols of n-channel and p-channel MOSFETs, respectively. P1, P2, … and V1, V2, … are the parameters and their values, respectively. L and W are the channel length and width, respectively. AD and AS are the drain and source diffusion areas. L is decreased by twice LD to get the effective channel length. W is decreased by twice WD to get the effective channel width. L and W can be specified on the device, the model, or on the .OPTION statement. ANALYSIS


.TRAN 0.1US 1MS 600US 750US ; Transient analysis .PROBE ; Graphics post-processor .OPTIONS ABSTOL = 1.00N RELTOL = 0.01 VNTOL = 0.1 ITL5 = 40000 .FOUR 25KHZ I(VY) ; Fourier analysis .END DC–DC Converters 263 The value on the device supersedes the value on the model, which supersedes the value on the .OPTION statement. AD and AS are the drain and source diffusion areas. PD and PS are the drain and source diffusion perimeters. The drain–bulk and source–bulk saturation cur- rents can be specified either by JS, which is multiplied by AD and AS, or by IS, which is an absolute value. The zero-bias depletion capacitance can be specified by CJ, which is multiplied by AD and AS, and by CJSW, which is multiplied by FIGURE 8.15 Plots for Example 8.4. (a) Transient plots, (b) frequency response. Time 640 us 680 us 720 us 760 us 800 us V(3) 0 V 25 V I(L1) I(L2) −5.0 A −2.5 A 0 A I(C1) −5.0 A −3.0 A −1.0 A 1.0 A − I(C2) −10 A 10 A SEL>> (a) C2 capacitor current C1 capacitor current L1 and L2 inductors currents Converter output voltage Frequency 100 Hz 1.0 KHz 10 KHz VP(3) −200 d −100 d 0 d SEL>> Phase V(3) 0 V 2.5 V 5.0 V (b) Magnitude (833.282, 6.8014) 1.0467 K, −162.085) 266 SPICE for Power Electronics and Electric Power, Second Edition The LEVEL-2 model, which can take into consideration various parameters, requires considerable CPU time for the calculations and could cause convergence problems. The LEVEL-3 model introduces a smaller error than the LEVEL-2 model, and the CPU time is also approximately 25% less. The LEVEL-3 model is designed for MOSFETs with a short channel. TABLE 8.2 (continued) Model Parameters of MOSFETs Name Model Parameter Unit Default Typical XQC Fraction of channel charge attributed to drain 1 DELTA Width effect on threshold 0 THETA Mobility modulation (LEVEL = 3) V−1 0 ETA Static feedback (LEVEL = 3) 0 KAPPA Saturation field factor (LEVEL = 3) 0.2 KF Flicker noise coefficient 0 1E−26 AF Flicker noise exponent 1 1.2 FIGURE 8.17 PSpice n-channel MOSFET model. (a) PSpice model, (b) DC model. •• • • • •• •• • • • • • • • G D D S RD RD RS Cgd Cgs Cbs Cgb Rs S Source RDS RDS B G Bulk Id Id Vgd Cbd Drain Gate B −+ Vgs −+ Vbd + + − Vbd +− Vbs +− Vbs +− − + − Vds Vds (a) PSpice model (b) Dc model DC–DC Converters 267 The parameters that affect the switching behavior of a BJT in power elec- tronics applications are L W VTO KP CGSO CGDO The symbol of a metal-oxide silicon field-effect transistor (MOSFET) is M. The name of a MOSFET must start with M and takes the general form M<name> ND NG NS NB MNAME + [L=<value] [W=<value>] + [AD=<value>] [AS=<value>] + [PD=<value>] [PS=<value>] + [NRD=<value>] [NRS=<value>] + [NRG=<value>] [NRB=<value>] where ND, NG, NS, and NB are the drain, gate, source, and bulk (or substrate) nodes, respectively. MNAME is the model name and can begin with any character; its word size is normally limited to eight characters. Positive current is the current that flows into a terminal. That it, the current flows from the drain node, through the device, to the source node for an n-channel MOSFET. 8.7 MOSFET PARAMETERS MOSFET as follows: + L=2U VTO=2.831 RD=1.031M RDS=444.4K CBD=3.229N PB=.8 MJ=.5 + CGSO=9.027N CGDO=1.679N RG=13.89 IS=194E–18 N=1 TT=288N) However, we shall generate approximate values of some parameters [8, 9]. From the data sheet we get IDSS = 250 µA at VCS = 0 V, VDS = 100 V. VTh = 2 to 4 V. Geometric mean, VTh = VTO = = 2.83 V. The constant Kp can be found from ID = Kp(VGS − VTh)2 (8.5) For ID = IDSS = 250 µA, and VTh = 2.83 V, Equation 8.5 gives Kp = 250 µA/2.832 = 31.2 µA/V2. Kp is related to channel length L and channel width W by (8.6) 2 4× K C W Lp a o=     µ 2 268 SPICE for Power Electronics and Electric Power, Second Edition where Co is the capacitance per unit area of the oxide layer, a typical value for a power MOSFET being 3.5 × 10−8 F/cm2 at a thickness of 0.1 µm, and µa is the surface mobility of electrons, 600 cm2/(V ⋅ sec). The ratio W/L can be found from Let L = 1 µm and W = 3000 µm = 3 mm Crss = 350 − 500 pF at VGS = 0, and VDS = 25 V. The geometric mean, Crss = Cgd = = 418.3 pF at VDG = 25 V. For a MOSFET, the values of Cgs and Cgd remain relatively constant with changing VGS or VDS. They are determined mainly by the thickness and type of the insulating oxide. Although the curves of the capacitances vs. drain–source voltage show some variations, we will assume constant capacitances. Thus, Cgdo = 418.3 pf and Ciss = 2000 to 3000 pF. The geometric mean Ciss = = 2450 pF. Because Ciss is measured at VGS = 0 V, Cgs = Cgso. That is, Ciss = Cgso + Cgd FIGURE 8.18 Data sheet for MOSFET of type IRF150. (Courtesy of International Rec- tifier.) 20.32 (0.800) Max. dia. Case style and dimensions 1.60 (0.063) Max. dia. Drain (case) Source Gate 26.67 (1.050) Max. Two places Two places 4.08 (0.161) 3.84 (0.151) Dia 5.71 (0.225)t 5.21 (0.205) Two places 1.60 (0.063) 1.45 (0.057) Dia. Seating plane 7.87 (0.310) 7.12 (0.280) 12.19 (0.480) 11.18 (0.440) 20.32 (0.800) Max. dia 39.96 (1.573) Max. 3.42 (0.135) Max. 17.14 (0.675)t 16.64 (0.655) 30.40 (1.197) 29.90 (1.177) 11.17 (0.440)t 10.67 (0.420) t measured at seating plane Conforms to JEDEC outline TO-204AE (modified TO-3) Dimensions in Millimeters and (Inches) 39.95 (1.573) Max. W L K C = = × × × × = − − 2 2 31 2 10 600 3 5 10 3 6 8 p a oµ . . 350 500× 2000 3000× DC–DC Converters 271 FIGURE 8.18 (continued). Z th JC (t )/ R th JC , N o rm al iz ed e ff ec ti ve tr an si en t th er m al i m p ed an ce ( p er u n it ) 0.01 10 −5 10 −4 2 5 10 −3 2 5 10 −2 2 t1, Square wave pulse duration (seconds) 5 10 −1 2 5 1.02 5 2 5 0.02 0.05 0.1 0.2 0.5 1.0 2 10 t2 t1 t1 t2 PDM 1. Duty factor, D = 3. TJM−TC = PDMZthJC(t). Notes: 2. Per unit base = RthJC = 0.83 deg. C/W. Single pulse (transient thermal impedance) D = 0.5 0.2 0.1 0.05 0.02 0.01 0 4 8 12 16 20 2 1.0 5 10 2 2 5 10 2 10 20 30 40 50 0 1 2 3 4 g ls , T ra n sc o n d u ct an ce ( si em en s) TJ = −55°C TJ = 150°CTJ = 150°CTJ = 25°C TJ = 25°C TJ = 25°C TJ = +125°C 80 µs pulse test VDS > ID(on) × RDS(on) max. Fig. 5–Maximum effective transient thermal impedance, junction-to-case vs. pulse duration Fig. 6–Typical transconductance vs. drain current ID, Drain current (amperes) 0.75 0.85 0.95 1.05 1.15 1.25 0 40−40 80 120 160 Fig. 8–Breakdown voltage vs. temperature Fig. 7–Typical source-drain diode forward voltage VSD, Source-to-drain voltage (volts) I D R , R ev er se d ra in c u rr en t (a m p er es ) R D S (o n ), D ra in -t o -s o u rc e o n r es is ta n ce (n o rm al iz ed ) B V D S S , D ra in -t o -s o u rc e b re ak d o w n v o lt ag e (n o rm al iz ed ) 0.2 0.6 1.0 1.4 1.8 2.2 0 40−40 80 120 Fig. 9–Normalized on-resistance vs. temperature TJ, Junction temperature (°C)TJ, Junction temperature (°C) VGS = 10 V ID = 14 A 272 SPICE for Power Electronics and Electric Power, Second Edition FIGURE 8.18 (continued). IRF150, IRF151, IRF152, IRF153 Devices 4000 20 15 10 5 40 32 24 16 8 0 0 3200 2400 1600 800 0.20 0.14 0.10 0.06 0.02 140 120 100 80 60 40 20 0 0 40 80 120 160 25 0 60 80 100 120 14020 40 50 75 100 125 150 10 VDS, Drain-to-source voltage (volts) ID, Drain current (amperes) I D , D ra in c u rr en t (a m p er es ) TC, Case temperature (°C) TC, Case temperature (°C) P D , P o w er d is si p at io n ( w at ts ) Qg, Total gate charge (nC) 20 30 40 50 28 56 84 112 140 C , C ap ac it an ce ( p F ) V G S , G at e- to -s o u rc e vo lt ag e (v o lt s) R D S (o n ), D ra in -t o -s o u rc e o n r es is ta n ce ( o h m s) Fig. 10–Typical capacitance vs. drain-to-source voltage Fig. 12–Typical on-resistance vs. drain current Fig. 13–Maximum drain current vs. case temperature Fig. 11–Typical gate charge vs. gate-to-source voltage Crss Coss Ciss Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + VGS = 0 f = 1 MHz CgsCgd Cgs + Cgd Cds + Cgd= VDS = 20 V VDS = 50 V VGS = 10 V VDS = 80 V, IRF150, 152 ID = 50 A For test circuit RDS(on), Measured with current pulse of 2.0 µs duration. Initial TJ = 25°C. (Heating effect of 2.0 µs pulse is minimal.) VGS = 20 V IRF150, 151 IRF152, 153 DC–DC Converters 273 which gives Cgso = Ciss − Csd = 2450 − 418.3 = 2032 pF = 2.032 nF. Thus, the PSpice model statement for MOSFET IRF150 is .MODEL IRF150 NMOS (VTO=2.83 KP=31.2U L=1U W=30M CGDO=0.418N CGSO=2.032N) The model can be used to plot the characteristic of the MOSFET. It may be necessary to modify the parameter values to conform with the actual character- istics. It should be noted that the parameters differ from those given in the PSpice library, because their values are dependent on the constants used in derivations. FIGURE 8.18 (continued). • • • • • • • • • • • • • • • Vary tp to obtain Required peak IL VGS = 10 V tp IL VDS EC E1 L 0.05 Ω E1= 0.5 BVDSS EC = 0.75 BVDSS Out tp EC E1 VDS +VDS (isolated supply) VDS VDD VGS RL −VDS ID Current regulator 3 µf D S OutD.U.T Current sampling resistor IG Current sampling resistor G 0.2 µf12 V battery Adjust RL to obtain specified ID Fig. 15–Clamped inductive test circuit Fig. 17–Switching time test circuit Fig. 19–Typical time to accumulated 1% failure *Fig. 20–Typical high temperature reverse bias (HTRB) failure rate TJ, Junction temperature (°C) TJ, Junction temperature (°C) Fig. 18–Gate charge test circuit Fig. 16–Clamped inductive waveforms Pulse generator 10 Ω source impedance 0 50 KΩ 1.5 mA Same type as out IL 1018 104 1.0 0.01 0.1 0.001 0.0001 103 102 10 1.0 1016 1014 1012 1010 108 106 50 60 70 80 90 100 120 140 50 60 70 80 90 100 120 140 t, T im e (s ec o n d s) R an d o m f ai lu re r at e (fi ts )VG = 6 V 99% UCL 23 FITs 90% UCL 60% UCL 8 V 10 V 12 V 14 V 16 V 18 V 20 V – App- rox age of earth – 1 mille- nium – 5 years – 1 year – 1000 hours % P er t h o u sa n d h o u rs *The data shown is correct as of April 15, 1984. This information is updated on a quarterly basis; for the latest reliability data, please contact your local IR field office. 276 SPICE for Power Electronics and Electric Power, Second Edition The PSpice plots of the instantaneous MOSFET voltage V(3), the input current has not reached the steady state. Figure 8.21(b) gives the resonant frequency of fres = 796.14 Hz at a resonant peak gain of Ao(peak) = 1.71. Note: The base drive voltage is reduced to 60 V. For a duty cycle of k = 0.6675, the average load voltage [1] is Vo(av) = Vs /(1 – k) = 5/(1 – 0.6675) = 15V (PSpice gives 13.0 V). The load voltage has not yet reached the steady-state value. 8.9 IGBT MODEL and as a BJT from the output side. The modeling of an IGBT is very complex [8]. and (2) equation model. The composite model connects the existing BJT and MOSFET models of PSpice in a Darlington configuration and uses their built-in behavior of the IGBT accurately. The equation model [16,17] implements the physics-based equations and models the internal carrier and charge to simulate the circuit behavior of the IGBT accurately. This model is complicated, often unreliable and computationally slow because the equations are derived from the complex semiconductor physics theory. Simulation times can be over ten times longer than for the composite model. There are numerous papers on SPICE modeling of IGBTs. Sheng [18] com- pares the merits and limitations of various models. Figure 8.22(c) shows the equivalent circuit of Sheng’s model [15], which adds a current source from the drain to the gate. The major inaccuracy in dynamic electrical properties [15] is associated with the modeling of the drain to gate capacitance of the n-channel MOSFET. During high-voltage switching, the drain-to-gate capacitance Cdg changes by two orders of magnitude due to any changes in drain-to-gate voltage Vdg. This is, Cdg is expressed by ANALYSIS


.TRAN 0.1US 2MS 1.8MS UIC ; Transient analysis with initial conditions .PROBE ; Graphics post-processor .OPTIONS ABSTOL = 1.00N RELTOL = 0.01 VNTOL = 0.1 ITL5 = 40000 .FOUR 25KHZ I(VY) ; Fourier analysis .END C C V qN C A dg si si dg B oxd dg si oxd = + ε ε ε 2 DC–DC Converters 277 FIGURE 8.21 Plots for Example 8.5. (a) Transient plots, (b) frequency response. Time (a) 1.80 ms 1.85 ms 1.90 ms 1.95 ms 2.00 ms AVG (V(3)) V(3) 0 V 15 V Average converter voltage (1.9727 m, 5.0394) V (5) 12 V 13 V 14 V SEL>> Load voltage I (VY) 0 A 1.0 A 2.0 A Input current Frequency (b) 10 Hz 100 Hz 1.0 KHz 10 KHz VP (3) −100 d 0 d Phase (2.2721K, −98.696) V (3) 0 V 1.0 V 2.0 V SEL>> Magnitude (796.141, 1.7143) 278 SPICE for Power Electronics and Electric Power, Second Edition PSpice Schematics does not incorporate a capacitance model involving the square root, which models the space charge layer variation for a step junction. PSpice model can implement the equations describing the highly nonlinear gate–drain capacitance into the composite model by using the analog behavioral modeling function of PSpice. The student version of the PSpice Schematics or OrCAD library comes with one breakout IGBT device, ZbreakN, and one real device, IXGH40N60. Although a complex model is needed for accurately simulating the behavior of an IGBT circuit, these simple PSpice IGBT models can simulate the behavior of a converter for most applications. The model parameters of the IGBT of IXGH40N60 are as follows: .MODEL IXGH40N60 NIGBT (TAU=287.56E-9 KP=50.034 AREA=37.500E-6 + AGD=18.750E-6 VT=4.1822 KF=.36047 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 EXAMPLE 8.6 PLOTTING THE OUTPUT AND TRANSFER CHARACTERISTICS OF AN IGBT Use PSpice to plot the output characteristics (VCE vs. IC) of the IGBT for VCE = 0 to 100 V and VGS = 4 V to 210 V. SOLUTION characteristics IC vs. VCE C G T 4.1049 V. An ZberakN device will permit adjustment of the model parameters. At a gate voltage less then the threshold voltage, the device remains off. (a) (b) (c) FIGURE 8.22 Equivalent circuits of IGBT SPICE moels. (a) n-type IGBT, (b) composite model, (c) Sheng PSpice model. Z1 ZbreakN MOSFET MOSFET G GM1 M1 Q1 Q1 Idg C C 6 5 0 4 PNP PNP E E DC–DC Converters 281 ances, the difference is approximately +0.5 V. For the output files, the sensitivity of each component on the output could be found. 8.10 LABORATORY EXPERIMENT The following two experiments are suggested to demonstrate the operation and characteristics of DC choppers: DC buck chopper DC boost chopper 8.10.1 EXPERIMENT TP.1 DC BUCK CHOPPER FIGURE 8.25 Worst-case and nominal output voltages for Example 8.7. Objective To study the operation and characteristics of a DC buck chopper under various load conditions. Applications The DC buck (step-down) chopper is used to control power flow in power supplies, DC motor control, input stages to inverters, etc. Textbook Apparatus 1. One BJT/MOSFET with ratings of at least 50 A and 500 V, mounted on a heat sink 2. One fast-recovery diode with ratings of at least 50 A and 500 V, mounted on a heat sink Time 3.90 ms 3.95 ms 4.00 ms V (Vx:-) 16 V 17 V 18 V SEL>> Nominal output YMAX output AVG (V (Vx:-)) 16 V 17 V 18 V YMAX average output Nominal average output 282 SPICE for Power Electronics and Electric Power, Second Edition 3. A firing pulse generator with isolating signals for gating the BJT 4. An RL load 5. One dual-beam oscilloscope with floating or isolating probes 6. DC voltmeters and ammeters and one noninductive shunt Warning Before making any circuit connection, switch the DC power off. Do not switch on the power unless the circuit is checked and approved by your laboratory instructor. Do not touch the transistor heat sinks, which are connected to live terminals. Experimental procedure 1. Set up the circuit as shown in Figure 8.26. Use a load resistance R only. 2. Connect the measuring instruments as required. 3. Set the chopping frequency to fc = 1 kHz and the duty cycle to k = 50%. 4. Connect the firing pulse to the BJT/MOSFET. 5. Observe and record the waveforms of the load voltage vo, the load current io, and the input current is. 6. Measure the average load voltage Vo(DC), the average load current Io(DC), the rms transistor current IT(rms), the average input current Is(DC), and the load power PL. 7. Repeat steps 2 to 6 with a load inductance L only. 8. Repeat steps 2 to 6 with both load resistance R and load inductance L. Report 1. Present all recorded waveforms and discuss all significant points. 2. Compare the waveforms generated by SPICE with the experimental results, and comment. 3. Compare the experimental results with the predicted results. 4. Calculate and plot the average output voltage Vo(DC) against the duty cycle. 5. Discuss the advantages and disadvantages of this type of chopper. FIGURE 8.26 BJT step-down chopper. Ls Is C1 Dm R1 R8 RS SW Fuse Vs = 100 V, dc + – A 2 μH V Dc VA DCDC L 25 mH R 50 Ω 50 Ω 10 Ω 250 Ω 0.1 μF 0.1 μF vg+ – Q1 Cs DC–DC Converters 283 8.10.2 EXPERIMENTAL TP-2 DC BOOST CHOPPER 8.11 SUMMARY The statements of BJTS are: Q<name> NC NB NE NS QNAME [(area) value] .MODEL QNAME NPN (P1=B1 P2=B2 P3=B3 … PN=VN .MODEL QNAME NPN (P1=B1 P2=B2 P3=B3 … PN=VN The statements for MOSFETs are M<name> ND NG NS NB MNAME + [L=<value] [W=<value>] + [AD=<value>] [AS=<value>] + [PD=<value>] [PS=<value>] + [NRD=<value>] [NRS=<value>] Objective To study the operation and characteristics of a DC boost chopper under various load conditions. Applications The DC boost (step-up) chopper is used to control power flow in power supplies, DC motor control, input stages to inverters, etc. Textbook See Reference 12, Section 5.4 and Section 5.7. Apparatus See Experiment TP.1. Warning See Experiment TP.1. Experimental procedure Set up the circuit as shown in Figure 8.27. Repeat the steps of Experiment TP.1. Report See Experiment TP-1. FIGURE 8.27 BJT step-up chopper. 286 SPICE for Power Electronics and Electric Power, Second Edition Average load current, Io(DC) = 2.5 A Peak-to-peak load ripple current should be less than 10% of the load average value, Io(DC) (a) Determine the ratings of all devices under worst-case conditions. (b) Use SPICE to verify your design. (c) Provide a cost estimate of the circuit. 8.4 (a) Design an output C filter for the chopper of Problem 8.3. The harmonic content of the output voltage should be less than 10% of the value without the filter. (b) Use SPICE to verify your design in part (a). 8.5 It is required to design a buck regulator with the following specifications: DC input voltage, Vs = 15 V Average output voltage, Vo(DC) = 10V Average load voltage, Io(DC) = 2.5 A Peak-to-peak output ripple voltage should be less than 50 mV Switching frequency, fc = 20 kHz Peak-to-peak inductor ripple current should be less than 0.5 A (a) Determine the ratings of all devices and components under worst- case conditions. (b) Use SPICE to verify your design. (c) Provide a cost estimate of the circuit. 8.6 It is required to design a boost regulator with the following specifications: DC input voltage, Vs = 12 V Average output voltage, Vo(DC) = 24 V Average load current, Io(DC) = 2.5 A Switching frequency, fc = 20 kHz Peak-to-peak output ripple voltage should be less than 50 mV Peak-to-peak inductor ripple current should be less than 0.5 A (a) Determine the ratings of all devices and components under worst- case conditions. (b) Use SPICE to verify your design. (c) Provide a cost estimate of the circuit. DC–DC Converters 287 8.7 It is required to design a buck–boost regulator with the following specifications: DC input voltage, Vs = 15 V Average output voltage, Vo(DC) = 10 V Average load current, Io(DC) = 2.5 A Switching frequency, fc = 20 kHz Peak-to-peak output ripple voltage should be less than 50 mV Peak-to-peak ripple current of inductor should be less than 0.2 A (a) Determine the ratings of all devices and components under worst- cast conditions. (b) Use SPICE to verify your design. (c) Provide a cost estimate of the circuit. 8.8 It is required to design a cuk regulator with the following specifications: DC input voltage, Vs = 15 V Average output voltage, Vo(DC) = 10 V Average load current, Io(DC) = 2.5 A Switching frequency, fc = 20 kHz Peak-to-peak ripple voltages of capacitors should be less than 50 mV Peak-to-peak ripple currents of inductors should be less than 0.2 A (a) Determine the ratings of all devices and components under worst- case conditions. (b) Use SPICE to verify your design. (c) Provide a cost estimate of the circuit. 8.9 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.1. 8.10 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.2. 8.11 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.3. 288 SPICE for Power Electronics and Electric Power, Second Edition 8.12 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.4. 8.13 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.5. 8.14 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.6. 8.15 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.7. 8.16 Assuming ±20% tolerances with standard deviations for all capacitors, inductors, and resistors, plot the worst-case average and instantaneous load voltages for Problem 8.8.