CHAPTER 9. DIODES and DIODE CIRCUITS, Exercises of Topology

Download CHAPTER 9. DIODES and DIODE CIRCUITS and more Exercises Topology in PDF only on Docsity! Circuits, Devices, Networks, and Microelectronics 183 CHAPTER 9. DIODES and DIODE CIRCUITS 9.1 INTRODUCTION TO SEMICONDUCTOR ELECTRONICS The earliest form of non-linear electronics was not based on semiconductor electronics but on devices in which the flow of electrons was contained within a vacuum envelope, or tube. Vacuum tubes were intricate and interesting, but were bulky, hard to make, and easily broken. And their cathode filaments had a limited lifetime. If we should wish to work in outer space where a vacuum is readily available they might make a resurgence. But here on the earth, with its oxygen-nitrogen atmosphere and the discovery that most electronics could be accomplished using semiconductors, vacuum tubes became an obsolescent artifact in the history of electronics. Semiconductors are interesting and unique in that they may be alloyed to provide an excess of charge carrier densities according to ‘doping’ levels of alloyed impurities. Furthermore the impurity alloying can be patterned using masks, particularly when the impurities can be injected and laid down by means of ion guns and molecular beams and other such weaponry. In addition to these aspects, impurity alloying invites the context of two types of charge-carriers, (1) electrons and (2) holes (what??). Excess electron densities afforded by ‘donor’ impurities speak for themselves. The nomenclature that we identify as ‘holes’ is peculiar to the fact that we are using a solid-state lattice as a medium which will accommodate the absence of an electron at the atomic sites defining the lattice. The absence of an electron represents a positive charge site that may be traded around with much of the same mobility as that of a conduction electron except with an electronic charge measure of +q instead of a –q measure. The secret, of course, is that semiconductors are a material that is neither metal nor insulator. They are characterized by a band-gap between (1) the valence energies that bind the crystal together and (2) the higher energies in which electrons are not bound but are (reasonably) free to roam throughout the material. The physics is entertaining, as most physics usually is. The band-gap context is shown by figure 9.1-1. If the band-gap is overly large (e.g. EG > 5 ev) the material is then an insulator. Figure 9.1-1. Band-gap context of semiconductors. Circuits, Devices, Networks, and Microelectronics 184 Notice that the higher-energy band is labeled as the ‘conduction’ band with lower band edge EC, since electrons at these energies are not strongly bound and can therefore be pushed around by the slightest of E-fields, much like the electrons within a metal. The context is even more emphatic when viewed as a lattice, such as that of Silicon, which is tetravalent, and therefore is bound (covalently) to four nearest neighbors as shown by figure 9.1-2. (a) Donor impurities under E-field (b) Acceptor impurities under E-field (movement of loose electrons) (movement of loose holes) Figure 9.1-2. The Si lattice in 2-dimensions, showing covalent (shared) electrons between atomic lattice nodes. (Actually the lattice is more like that of figure 9.1-4 (a) for which four nearest neighbors are at tetrahedral vertices.) The two-dimensional representation is most informative since we can look upon the semiconductor in terms of the effect of appropriate impurities. For example, as shown by the figure, if a phosphorus (pentavalent) impurity is introduced into the lattice, its extra valence electron becomes a step-child. It is therefore prone to depart and wander around the neighborhood. On the other hand if a boron (trivalent) impurity is introduced within the lattice it leaves a ‘hole’ (hence the name). And the hole will skip from one site to the next as neighboring covalent electrons fall into it and leave an absence (hole) at their former home site. Once again the physics is fun, particularly when the lattice structure is introduced, for which the simple band-gap context takes on a periodic geometric context. But the context is still relatively simple. A hole is very much like the little bubblets that you will see when you drop by your local tavern for a tall cold ginger ale. Notice that bubblets fall upward, whereas pellets fall downward. In the context of semiconductors the gravitational field would be replaced by an electric field for which ‘holes’ are equivalent to bubblets and the electrons are equivalent to pellets. Circuits, Devices, Networks, and Microelectronics 187 field that blocks any further migration of charge across the junction boundary. The built-in field context is a signature of the junction and is represented by figure 9.2-2. Figure 9.2-2. Uncovered impurity sites in the vicinity of the pn junction boundary This behavior reveals another context of semiconductors, namely that they accommodate the presence of an electric field, much like an insulator. In the vicinity of a pn junction the thermal statistics induces an E-field strong enough to crackle were it outside the material. And yet the semiconductor material away from the junction contains sufficient mobile charge carrier densities for good conduction. Since the two opposite polarity uncovered layers (also designated as the space-charge layer) thickness is on the order of microns the junction E-field is huge. Consider the following example: EXAMPLE 9.2-1: An abrupt junction has a density of (acceptor)(p-type) impurities of NA = 1016 #/cm3 and a density of (donor)(= n-type) impurities of ND = 1015 #/cm3. (This is called a one-sided junction and is reflected by the illustration). The field develops a voltage difference due to the band-gap of  = 0.8V which uncovers the doping sites to a layer thickness of 0.18m on the p-side and 1.8m on the n-side. (Notice that this gives charge equilibrium). What is the magnitude of the electric field in V/cm? Figure E9.2-1: Example slice across an abrupt (idealized) pn junction. Note that charge equilibrium requires that the more lightly-doped uncovered charge layer be much thicker than that for the more heavily doped side. The donor impurities have density ND = 0.1 × NA and so Wn = 10 × Wp. SOLUTION: The average separation of charge = 0.5 × (Wp + Wn) = 0.5 × (0.18 + 1.8)m = 1.0m. The E-field is then = (0.8V/1.0m) = 0.8 V/m = 0.8 × 104 V/cm. = 8.0 kV/cm Circuits, Devices, Networks, and Microelectronics 188 Example E9.2-1 points out that the intrinsic electric field due to the uncovered charge sites in the vicinity of the metallurgical junction is anything but small. This large E-field then serves to block any further migration (= diffusion) of charge across the junction boundary. However if we should lower the electric field by means of a forward voltage bias (Vp – Vn) > 0 the thermal diffusion pressures will cause charge carriers to flood across the junction. Diffusion is a thermal process defined by thermal statistics. The thermal flood has an exponential behavior relative to the quantized thermal energy kT and therefore the charge carrier flow will also be exponential relative to kT/q, as indicated by figure 9.2-2 and by equation (9.2-1). If Vpn < 0 (which we also call reverse-bias) the E-field barrier becomes larger and continues to block the diffusion of charge carriers across the junction boundary. (a) I (V) on linear scale. (b) I (V > 0) on logarithmic scale. Figure 9.2-2. I vs V characteristics of the pn junction (= pspice rendition of the 1n914 general-purpose high-speed switching diode). Figure 9.2-2(b) shows that the slope is approximately linear on the logarithmic scale, which is consistent with the exponential behavior of charge carriers flooding across the forward-biased junction. The basic mathematical form of this response is given by the ideal diode equation  1 TnVV S eII (9.2-1) where VT is defined as the thermal voltage and IS is identified as the reverse saturation current. The voltage V is the same as Vpn, otherwise called the forward voltage. The thermal voltage relates to the quantized thermal energy kT as qkTVT  (9.2-2) Where k = Boltzmann constant = 8.62 × 10-5 eV/K and q = magnitude of the electronic charge = 1.602 × 10-19C = 1.0eV/J. At nominal room temperature 295K the thermal voltage is then Circuits, Devices, Networks, and Microelectronics 189 VT (at T = 25oC) = .0254 V V025. (9.2-3) The thermal voltage is given an equation number all of its own because the value VT = .025V is employed for most back-of-the-envelope calculations. The parameter n is called the emission coefficient and is the principal reason why the ideal diode equation is not linear for the entire region of I(V > 0). In the vicinity of the most likely region of operation 0.7V < V < 0.9V , emission coefficient n approximately = 1. For lower voltages n = 2 (approximately). For voltages higher than 1.2V the resistance of the semiconductor material begins to dominate and the I(V) is linear rather than exponential (which shows up as a roll-off on the logarithmic scale). It should be apparent that the circuit simulator is using more comprehensive mathematical models than just equation (9.2-1) to provide the best possible representation of the diode. So the ideal diode equation is only the first-order part of the story. The electrical behavior of the junction when it is employed as a circuit component suggests the symbol shown by figure 9.2-3(b). It looks like an arrowhead that points in the direction of forward (also called the ‘easy’) current flow, consistent with figure 9.2-2. Figure 9.2-3. Physical context and circuit symbol for pn junction (diode). To be fair, minority-carrier current does flow in the reverse-bias direction. It even increases a tad as the reverse bias is increased (as must always be true). It is important to note that reverse-bias current is on the order of IS = 10-15A = 1.0 fA, depending on the area of the junction. This level of current is less than that for many insulators of like area and tells us that the reverse-biased junction is effectively a very good insulator. For the 1n914 diode IS = 16.8 × 10-20A, which is about two orders of magnitude smaller than the conductance of the air in the vicinity of the diode. The symbolic context also identifies that the junction in reverse-bias is a capacitance, inasmuch as there is a separation of charge and virtually no leakage current. But the junction is also more than a simple plate capacitance because a greater reverse-bias increases the built-in field and uncovers more charge. Hence the layer thicknesses Wn and Wp increase proportionally and therefore the capacitance decreases with the application of more voltage. Circuits, Devices, Networks, and Microelectronics 192 Although the example was simple and direct it also suggests that the voltage loop and DC voltage source are an aside to the rest of the circuit and may be treated as ideal batteries with short-circuit current able to forge a wrench or melt down a battleship if so desired. As a simplification the voltage sources will be replaced voltage supply ‘rails’, much like we might see if we laid the circuit components down on a printed circuit board or within an integrated circuit. And that brings us to another example, just like that of example 9.3-1, except different. EXAMPLE 9.3-2: Diodes between voltage rails and analysis by inspection. Find I2 and V2. By inspection I2 = 0.1mA V2 = 4.0V (or otherwise if not, then)    4010 7.024.6 2   I = 0.1 mA 7.024.01002 V = 4.0 V Figure E9.3-2. Diode string and analysis by inspection The solution context ‘by inspection’ should not be unfamiliar and truly is the only practical way to do most aspects of circuit analysis. The CVD and the ideal rectifier model permit us to cut to the chase ‘by inspection’ and acquire values of the electrical facts without cluttering up the analysis with arithmetic. But also consider that we are dealing with junction diodes that clearly have two ‘states’ (ON and OFF). The previous examples made the visual assumption that the diodes were ‘ON’ and that guided the process. The‘OFF’ state was not considered. But if you were blind you would have to do so, or identify a bias criterion for the ON/OFF state of the diode component. The bias assessment is therefore a part of the inspection analysis just as much if not more than the rough mathematical analysis. Consider the following example Circuits, Devices, Networks, and Microelectronics 193 EXAMPLE 9.3-3: A diode string between voltage dividers. Find V1, V2 and ID. Figure E9.3-3. Diode string and resistance network. SOLUTION: If you look at the voltage dividers to each side of the diode string it should be evident that V1 is greater than V2 by inspection since the naked voltage dividers would give V1 = 6.67V and V2 = 2.0V. You do not need the naked values for V1 and V2 to affirm that the diode string has no choice but to be conducting. You could even hazard a WAG (wild-eyed guess) as to what voltage values would result since V1 will be pulled down by the diode current and V2 will be pulled up. In the analysis of electronic circuits with non-linear elements, even a WAG may be adequate, - even on a quiz, if within 10%. Turning to mathematics and nodal analysis at V1 and V2, respectively, we get V1:   0105.025.05.01  DIV and V1 = V2 + 2 × 0.7 V2:   01025.00.125.02  DIV --------------------------------------------------------     01025.05.075.04.125.175.02 V So that   0.2 05.15.7 2  V = 3.23 V V1 = 3.23 + 1.4 = 4.62 V And from the V2 node equation:   1025.00.125.02 VI D = 1.53mA The network mathematics invited the use of nodal analysis. Nodal analysis gives node voltages. Circuit simulation software accomplishes its assessment by a modified nodal analysis. But even the circuit simulation software has to make a perceptive preliminary assessment of the node voltages before undertaking its iterative numerical analysis. Diode characteristics and that of their semiconductor cousins are defined by voltage biases. So options on the voltage states are an essential part of the assessment. The rest of the story is associated with effect of Circuits, Devices, Networks, and Microelectronics 194 the resistance paths on the node voltages, and the inspection process give the preliminary assessment and identifies which states are true. Consider the following example EXAMPLE 9.3-4: Determine ID1, ID2 and V4. For: (a) R1 = 4.0, R2 = 1.0 (k) (b) R1 = 1.0, R2 = 4.0 (k) Figure E9.3-4. Two diodes and resistance network. SOLUTION: Examine the possibilities. Note that diode D2 must always be ON since it is oriented correctly for current passing through R2 and does not care what R1 and R2 might be. (a) For R1 = 4.0 and R2 = 1.0 (k) it appears by inspection that V4 will be sufficiently negative so that D1 will be OFF. And therefore the current through the string must be    0.10.4)5(7.052 DI = 1.86 mA Which makes V4 = 5 + 1.86 × 1.0 = -3.14 V And this makes the voltage Vx (penciled in) = -2.44 V *And this confirms that diode D1 is non-conducting, since it is in reverse bias, just like we presupposed. So ID1 = 0.0mA (b) For R1 = 1.0 and R2 = 4.0 (k) it appears by inspection that V4 will be sufficiently positive so that it is expected that D1 will be ON. And therefore voltage V4 = 0.0V, and the current through R2 will be 22 DII  = 1.25 mA (by inspection) and also Vx (penciled in) = 0.7V and therefore the current through R1 will be ID2 = (5 – 0.7)/1.0 = 4.3mA Circuits, Devices, Networks, and Microelectronics 197 9.4 DIODE RECTIFIERS CIRCUITS and AC-DC CONVERTERS One of the earliest usages of the diode was energy conversion, specifically AC- to –DC. Early in the history of the power grids it became evident (via the War of Currents) that alternating voltages were the best way to transmit power over distance, whereas the best form of locally useful energy was a fixed voltage source supplying a direct current (DC). Most electronic circuits use a single pole (DC) polarity in the form of voltage rails. So for a distribution system that uses an AC grid, the diode component is made to order for the AC-DC conversion, whether it be a vacuum diode or a pn junction. The concept is shown by figure 9.4-1. Figure 9.4-1(a). Series diode and load, also called a half-wave rectifier (HWR). When Vs < 0 the current flow is blocked by the ‘OFF’ state of the diode. Figure 9.4-1(b). Voltage across the load due to IL . A resistance load is always elected because it is a dissipative element. The average voltage for figure 9.4-1(b) is                   0 2 0 0sin 2 11 )( ddVdttV T tV L T L LV  1 (9.4-1) and the average power delivered to the load is L L L R V tP 2 2 1 )(   L L R V 2 1.0 (9.4-2) It is always in order to include a transformer input coupling as shown by figure 9.4-1(a) both for (1) isolation and for (2) control of the voltage amplitude at the secondary = VS. If VS is less than 10V it is in order to include a diode drop, even though accuracy is not that critical in the art of electronics. The rest of the story is that there is another quick AC-DC option using four diodes (affectionally called a diode bridge) as shown by figure 9.4-2(a). Circuits, Devices, Networks, and Microelectronics 198 Figure 9.4-2(a). Diode bridge and load, also called a full-wave rectifier (FWR). Figure 9.4-2(b). Voltage across the load due to current through the diodes for the FWR (a.k.a. FWB). Note that the contribution to IL comes from both polarities (1) the conductive loop through D1 and D2 formed when Vs > 0 and (2) the conductive loop through D3 and D4 when Vs < 0. The outcome is shown by Figure 9.4-2(b) The FWR topology may also be drawn in bridge form shown by figure 9.4-5. Figure 9.4-3 Full-wave rectifier (FWR) topology of figure 9.4-2(a) drawn as a full-wave bridge (FWB). Compare the position of the diodes between this figure and that of figure 9.4-2(a) And the same mathematics applies to the FWR as equation (9.4-1) except there are two half waves that add up to give a factor of two   LL VtV   2 (9.4-3) for which the average power delivered to the load is L L L R V tP 2 2 4 )(   L L R V 2 4.0 (9.4-4) Circuits, Devices, Networks, and Microelectronics 199 Average current through RL identifies one-one with the count of rectified half-waves. So if the source is three-phase (3) then the count of half-waves across RL is three and the current is of the form represented by figure 9.4-4. Figure 9.4-4. Three-phase sum of rectified currents. The outcome shows up as a steady-state signal with a ripple of peak-peak amplitude VR and frequency = 6 × f0 . The averaged output level for the 3 rectifier is then   LL VtV   3 (9.4-5) and the power to the load is L L L R V tP 2 2 9 )(   L L R V 2 91.0 (9.4-6) The output voltage level VL, as well as being close to unity, is also one for which the ripple is small and mathematically of the value LL VV  134.0 = VR (9.4-7) Equations (9.4-5) through (9.4-7) point out an aspect of the AC-DC converter that is of importance, namely an output that is as much like an ideal voltage rail as possible. Ripple VR needs to be small, and that invites the use of a few modifications to single-phase AC-DC converters, as represented by figures 9.4-5(a) and 9.4-5(b) Circuits, Devices, Networks, and Microelectronics 202 SOLUTION: The voltage across the load is VL = VZ + VD = 6.8 + 0.7 = 7.5V So the current drawn by the application is IL = PL/VL = 300mW/7.5V = 40mA Therefore the minimum current that must be supplied by the source = IL + IZ(min) = 40mA + 5mA = 45mA Vbat(min) must be able to supply 45mA through RS , which must then be RS = [Vbat(min) – VL]/IS(min) = ( 12 – 7.5)/45mA = 0.1 k = 100 The worst-case power dissipated through the Zener diode is when Vbat = Vbat(max) and the load is OFF. The current that flows through RS will be IS(max) = (15 – 7.5)/0.1k = 75 mA All of this current will flow through the Zener diode when the application is OFF and therefore PL(worst) = 6.8V x 75mA = 510mW = 0.51W Take note from the example that the Zener diode must always have a drop-down resistance, both because it is required that VZ < V(source) and because the RS is needed to limit the current through the zener diode. This context is represented in a more typical use of a Zener diode in context with an AC-DC converter topology as shown by example 9.4-2 EXAMPLE 9.4-2: For the FWR topology shown choose component values that will support a Zener regulated 240mW, 6V application from a 120V 60Hz power tap. Transformer turns ratio n12 = 12:1. Assume all diode are Si power diodes (VD = 0.8V) Figure E9.4-2 Full-wave rectifier AC-DC Zener-regulated charging plug. (a) Determine VC and VP Circuits, Devices, Networks, and Microelectronics 203 (b) If VC(min) = 8.0V with the load connected, what values of R1 and C1 are required, assuming that the current through the Zener diode approaches zero when VC approaches VC(min). (c) What average power must the Zener diode dissipate when the load is not connected? SOLUTION: (a) Since 120V is rms then VP = 12 1 12022 2 1  n n Vrms = 14.1V and VC = VP – 2 x VD = 14.1 – 2 x 0.8 = 12.5V The characteristics of the load are PL = 240 mW at 6.0V, so IL = 240mW/6.0 = 40 ma and RL = 6.0V/40mA = 150  and from the requirement that VC(min) be able to provide IL + IZ(min) = 40mA + 0, then RS will be RS = [VC(min) – VL]/IS(min) = (8.0 – 6.0)/40mA = 50  Since the ripple VR = [VC(max) – VC(min)] = 12.5 – 8 = 4.5V and the resistance load to the capacitance R = RS + RL = 150 + 50 = 200 Then, from equation (9.4-10b)   fRVVC RC5.0    200605.45.125.0  = 116F The power dissipated in the Zener diode when the load is not connected is an average between the situation for which VC = 12.5V and VC = 8.0V. When VC = 8.0V then IZ = IL ( = IS (min) ) = 40mA since in the absence of a load all of the current must go through the Zener. When VC = 12.5V then the current through the drop-down resistance RS will be Is(max) = [VC(max) – VL]/RS = [12.5 – 6.0]/50 = 130 mA The average current that the zener diode must accommodate = [IS(max) + IS(min)]/2 . Since the Zener diode is in series with a junction diode then the Zener voltage has to be VZ = VL – VD = 6.0 – 0.8 = 5.2V and so the averaged power that it must be able to accommodate is     2(min)(max) SSZZ IIVtP  = 5.2 × [130 + 40]/2 = 442mW Circuits, Devices, Networks, and Microelectronics 204 If you held the patent on the circuit topology used in example 9.4-2 you could probably claim royalties of about 10 cents on each instance, regardless of their external shape. At least 20% of the people on the planet, to include children, have at least one of these circuits associated with their cell phone, laptop, or toy. They probably also buy a new one every year. There are about 6B people in the world So the patent holder could claim a royalty stream of $.10 × 20% × 6B / yr = $120M/yr. Unfortunately the patent on this topology has long expired. But this sort of circuit construct and patent analysis is what engineers are tasked to do. 9.5 DIODE-CAPACITANCE CIRCUITS The most interesting circuits in the diode kingdom are those in which a capacitance is involved. That might seem a little strange since there are only two basic circuits, one of which is the peak detector, shown by figure 9.5-1. Figure 9.5-1. Peak detector And the other of which is the level-shifter, shown by figure 9.5-2. Figure 9.5-2. level shifter The peak detector captures the peak. And if the source is sinusoidal, as in the previous section, it will capture the peak voltage and hold it as charge stored on the capacitance. If a load is included as in figure 9.4-5(a) the charge will discharge through the load until it is renewed by the next peak. Circuits, Devices, Networks, and Microelectronics 207 SOLUTION: VN needed to achieve ½ × (30kV/cm) is VN = 15kV/cm × 0.02cm = 300V The voltage achieved across each stage = VC = 2(VP – VD) = 2(2.2 – 0.7) = 3.0V And therefore the number of stages needed is N = VQ/VC = 100 stages The energy released on discharge is WQ = ½ × CQVQ 2 = 0.5 × .01F × 3002 = 0.45mJ The number of cycles to charge up capacitance CQ is n = N2CQ/2CP = 1002 × .01F/(2 × 50pF ) = 106 and so the time it takes to charge up the capacitance is T = t × n = (1/f) × n = 106/12.5MHz = 0.08 s The level shifter topology of figure 9.5-2 can be made considerably more flexible as is shown by figure 9.5-6 Figure 9.5-6. Adjustable level shifter If Vs is a square wave and the RC time constants are long, then the output is reasonably stable and has relatively little sag, as represented by figure 9.5-7 Figure 9.5-7. Adjustable level shifter, square-wave input. The input square wave is the dashed trace, 5V amplitude. R1 = 40k, R2 = 10 kC = .02F and f = 45kHz. For a square-wave output the new output levels will be V1 and –V2 . At equilibrium the quantity of charge added and subtracted to the capacitance must balance, i.e. Q+ = Q-, where Circuits, Devices, Networks, and Microelectronics 208 P D T T R VV dtIQ P 2 2 0 2    (9.5-6a) P D T T T R VV dtIQ P P 1 1 2 1    (9.5-6b) And so 21 1 2 1 2    R R VV VV D D (9.5-7) Where VD = diode drop. And since |V1| + |V2| = 2VP, with VP = peak of the input square wave then    211 12  DPD VVVV (9.5-8) Which is the same as     DDP VVVV  211 12  And then the shift in the output V is      DPDPP VVVVVVV  211 12  (9.5-9)      21 21 1 1      DP VVV (9.5-10) EXAMPLE 9.5-2: For an input square wave of VP = 5V amplitude, R1 = 40k, R2 = 10 kdetermine the level shift assuming that the capacitance is large enough to avoid sag in the waveforms for the frequency of interest. Assume VD = 0.7V. SOLUTION: a21 = 10k/40k = 0.25 And by equation (9.5-10)      25.01 25.01 7.05   V = 2.53 V Example 9.5-2 and figure 9.5-7 make use of the same component values and the V shift indicated by figure 9.5-7 is consistent with the numerical result of example 9.5-2. Circuits, Devices, Networks, and Microelectronics 209 The shift is also dependent on the waveform, as may be illustrated by the option for which VS is a triangular waveform as shown by figure 9.5-8. Figure 9.5-8. Adjustable level shifter, triangular-wave input representation. Equations (9.5-6a) and (9.5-6b) then become 1 2 2 2 0 2 2 1 t R VV dtIQ D t     (9.5-11a) 2 1 1 2 0 2 2 2 t R VV dtIQ D t     (9.5-11b) For which the balance, i.e. Q+ = Q- gives 1 2 2 1 1 2 R R t t VV VV D D    (9.5-12) But from figure 9.5-8 and the similar triangles 1 2 2 1 V V t t  (9.5-13) When this is translated into the current pushed by V1 and V2 through the diode for which V1 would be replaced by V1 – VD and V2 would be replaced by V2 – VD then 1 2 2 1 2 R R VV VV D D           (9.5-14) Circuits, Devices, Networks, and Microelectronics 212 Figure 9.6-1b. Sinusoidal signal transfer for the transfer curve of figure 9.6-1a You already know of this circuit as that of the half-wave rectifier topology. The transfer curve is a consequence of a breakpoint at Vin = 0. For Vin (t) < 0 the slope dVout/dVin = 0, which also correspond to the ‘OFF’ state of the diode. For Vin (t) > 0 the slope dVout/dVin = 1 and the Vout is a copy of the input. The Zener diode also serves as a means to achieve breakpoints, usually at higher bias voltages as illustrated by figures 9.6-2a and 9.6-2b. Figure 9.6-2a. Modification of figure 9.6-1a to include a 1n750 Zener diode (VZ = 4.7V). Figure 9.6-2b. Pspice rendition of figure 9.6-2a, showing (1) transfer curve and (2) Vout result for sinusoidal input with VP = 8.0V. The resulting output waveform is (roughly) a set of trapezoidal pulses. If one waveform is shaped from another then the two dissimilar waveforms will automatically be coherent. This is represented by example 9.6-1 Circuits, Devices, Networks, and Microelectronics 213 EXAMPLE 9.6-1: Use a wave-shaping network to reshape a triangular-wave input to a sinusoidal form using a diode-waveshaping network. SOLUTION: Since the output must be shaped for both polarities of the input waveform a full-wave option is necessary as represented by figure E9.6-1 Figure E9.6-1a. Use of diode bridge with in750 Zener diodes to create a clipper breakpoint at approximately 10.0 V. Figure E9.6-1b. pspice rendition of (1) waveshaping transfer curve (2) output waveform as shaped from triangular-wave input. Note that the construct essentially forms a simple voltage divider with  VRzR VRz V V IN OUT   1 )( (E9.6-1) and for V < Vbreak, Rz(V) = ∞ and consequently the ratio = 1.0 (and slope = 1.0). The output result is also a consequence of an informed choice of amplitudes for (1) the triangular wave input and (2) the resulting sinusoidal output. This amplitude is predicated on the context that both waveforms should have the same slope at t = 0. For the triangular waveform Circuits, Devices, Networks, and Microelectronics 214   T T t fV T V dt dV 4 40   TfV4 (E9.6-1) and for the sinusoidal waveform      0 0 cossin    tPP t tVtV dt d dt dV  PfV2 (E9.6-2) For these slopes to be equal then it is therefore necessary that 2   P T V V (E9.6-3) For the two 1n750 diodes in series with the generic ( = 1n914) diodes the peak voltage VP0 is approximately 10.0 and so the required amplitude for the triangular wave is PT VV  2  = 15.7 V The options on wave shaping circuits are a matter of choice. For passive circuit components as have been represented heretofore there are innumerable options, all of which will form breakpoints from one slope to another, with the caveat that all slopes are ≤ 1.0. If active elements (e.g. opamps, transistors ) are included then transfer slopes > 1.0 are also feasible, but are subject to constraints imposed by power supply rails and by the non-linearities of the active elements (transistor set).