Circuit and microelectronic devices formula sheet, Cheat Sheet of Microelectronic Circuits

Download Circuit and microelectronic devices formula sheet and more Cheat Sheet Microelectronic Circuits in PDF only on Docsity! 1 6.012 Microelectronic Devices and Circuits Formula Sheet for the Final Exam, Fall 2009 Parameter Values: Periodic Table: ! q = 1.6x10 "19 Coul # o = 8.854x10 "14 F/cm # r,Si = 11.7, #Si $10 "12 F/cm n i Si@R.T[ ] $10 10 cm "3 kT /q $ 0.025V ; kT /q( ) ln10 $ 0.06V 1µm =1x10 "4 cm ! III IV V B C N Al Si P Ga Ge As In Sn Sb Drift/Diffusion: Electrostatics: ! Drift velocity : s x = ±µm Ex Conductivity : " = q µen + µh p( ) Diffusion flux : Fm = #Dm $Cm $x Einstein relation : Dm µm = kT q ! " dE(x) dx = #(x) E(x) = 1 " #(x)dx$ % d&(x) dx = E(x) &(x) = % E(x)dx$ %" d 2&(x) dx 2 = #(x) &(x) = % 1 " #(x)dxdx$$ The Five Basic Equations: ! Electron continuity : "n(x, t) "t # 1 q "Je (x, t) "x = gL (x, t) # n(x,t) $ p(x,t) # ni 2[ ]r(T) Hole continuity : "p(x, t) "t + 1 q "Jh (x, t) "x = gL (x, t) # n(x,t) $ p(x,t) # ni 2[ ]r(T) Electron current density : Je (x, t) = qµen(x, t)E(x,t) + qDe "n(x,t) "x Hole current density : Jh (x, t) = qµh p(x, t)E(x,t) # qDh "p(x,t) "x Poisson's equation : "E(x,t) "x = q % p(x, t) # n(x, t) + Nd +(x) # Na #(x)[ ] Uniform doping, full ionization, TE ! n - type, Nd >> Na no " Nd # Na $ ND, po = ni 2 no, %n = kT q ln ND ni p - type, Na >> Nd po " Na # Nd $ NA , no = ni 2 po , %p = # kT q ln NA ni Uniform optical excitation, uniform doping ! n = no + n' p = po + p' n' = p' dn' dt = gl (t) " po + no + n'( )n'r Low level injection, n',p'<< po +no : dn' dt + n' #min = gl (t) with #min $ por( ) "1 2 Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and low level injection; p-type example): ! Minority carrier excess : d 2 n'(x) dx 2 " n'(x) Le 2 = " 1 De gL (x) Le # De$ e Minority carrier current density : Je (x) % qDe dn'(t) dx Majority carrier current density : Jh (x) = JTot " Je (x) Electric field : Ex (x) % 1 qµh po Jh (x) + Dh De Je (x) & ' ( ) * + Majority carrier excess : p'(x) % n'(x) + , q dEx (x) dx Short base, infinite lifetime limit: ! Minority carrier excess : d 2 n'(x) dx 2 " # 1 De gL (x), n'(x) " # 1 De gL (x)dxdx$$ Non-uniformly doped semiconductor sample in thermal equilibrium ! d 2"(x) dx 2 = q # ni e q" (x ) kT $ e$q" (x ) kT[ ] $ Nd (x) $ Na (x)[ ]{ } no(x) = nie q" (x ) kT , po(x) = nie $q" (x ) kT , po(x)no(x) = ni 2 Depletion approximation for abrupt p-n junction: ! "(x) = 0 #qNAp qNDn 0 for for for for x < #xp #xp < x < 0 0 < x < xn xn < x $ % & & ' & & NApxp = NDnxn (b ) (n #(p = kT q ln NDnNAp ni 2 w(vAB ) = 2*Si (b # vAB( ) q NAp + NDn( ) NApNDn Epk = 2q (b # vAB( ) *Si NApNDn NAp + NDn( ) qDP (vAB ) = #AqNApxp vAB( ) = #A 2q*Si (b # vAB( ) NApNDn NAp + NDn( ) Ideal p-n junction diode i-v relation: ! n(-xp ) = ni 2 NAp e qvAB / kT , n'(-xp ) = ni 2 NAp e qvAB / kT "1( ); p(xn ) = ni 2 NDn e qvAB / kT , p'(xn ) = ni 2 NDn e qvAB / kT "1( ) iD = Aqni 2 Dh NDnwn,eff + De NApwp,eff # $ % & ' ( eqv AB / kT -1[ ] wm,eff = wm " xm if Lm >> wm Lm tanh wm " xm( ) Lm[ ] if Lm ~ wm Lm if Lm << wm ) * + , + qQNR,p -side = Aq n'(x)dx, -wp -x p - qQNR ,n -side = Aq p'(x)dx, Note : p'(x) . n'(x) in QNRs xn wn - 5 Switching times and gate delay (full velocity saturation): ! "Ch arg e = "Disch arg e = CLVDD WminssatCox * VDD #VTn[ ] CL = n WnLn +WpLp( )Cox * = 2nWminLminCox * assumes ssat ,e = ssat,h "Min.Cycle = "Ch arg e + "Disch arg e = 4nLminVDD ssat VDD #VTn[ ] Dynamic power dissipation per gate (full velocity saturation): ! Pdyn@ f max = CLVDD 2 f max " CLVDD 2 #Min.Cycle " ssatWmin $oxVDD VDD %VTn[ ] tox PDdyn@ f max = Pdyn@ f max InverterArea " Pdyn@ f max W min L min " ssat$oxVDD VDD %VTn[ ] toxL 2 Static power dissipation per gate ! Pstatic =VDD ID,off "VDD W min L min µe Vt 2 #SiqNA 2 VBS e $VT{ } nVt PDstatic = Pstatic Inverter Area % VDD L min 2 µe Vt 2 #SiqNA 2 VBS e $VT{ } nVt CMOS Scaling Rules - Constant electric field scaling ! Scaled Dimensions : Lmin " Lmin s W "W s tox " tox s NA " sNA Scaled Voltages : VDD "VDD s VBS "VBS s Consequences : Cox * " sCox * K" sK VT "VT s # " # s Pdyn " Pdyn s 2 PDdyn@ fmax " PDdyn@ fmax PDstatic " s 2 e s$1( )VT snVt PDstatic Device transit times ! Short Base Diode transit time : " b = w B 2 2Dmin,B = w B 2 2µmin,BVthermal Channel transit time, MOSFET w.o. velocity saturation : " Ch = 2 3 L 2 µ Ch V GS #V T Channel transit time, MOSFET with velocity saturation : " Ch = L s sat 6 Small Signal Linear Equivalent Circuits: • p-n Diode (n+-p doping assumed for Cd) ! gd " #iD #vAB Q = q kT IS e qVAB / kT $ q ID kT , Cd = Cdp + Cdf , where Cdp (VAB ) = A q%SiNAp 2 &b 'VAB( ) , and Cdf (VAB ) = q ID kT wp ' xp[ ] 2 2De = gd( d with ( d " wp ' xp[ ] 2 2De • BJT (in FAR) ! gm = q kT "oIBS e qVBE kT 1+ #VCE[ ] $ q IC kT , g% = gm "o = q IC "o kT go = "oIBS e qVBE kT +1[ ] # $ # IC or $ IC VA & ' ( ) * + C% = gm, b + B-E depletion cap. with , b - wB 2 2De , Cµ : B-C depletion cap. • MOSFET (strong inversion; in saturation, no velocity saturation) ! gm = K VGS "VT (VBS )[ ] 1+ #VDS[ ] $ 2K ID go = K 2 VGS "VT (VBS )[ ] 2 # $ # ID or $ ID VA % & ' ( ) * gmb = +gm = + 2K ID with + , " -VT -vBS Q = 1 Cox * .SiqNA q/p "VBS Cgs = 2 3 W LCox * , Csb ,Cgb ,Cdb : depletion capacitances Cgd =W Cgd * , where Cgd * is the G-D fringing and overlap capacitance per unit gate length (parasitic) • MOSFET (strong inversion; in saturation with full velocity saturation) ! gm = W ssat Cox * , go = " ID = ID VA , gmb = #gm with # $ % &VT &vBS Q = 1 Cox * 'SiqNA q(p %VBS Cgs =W LCox * , Csb ,Cgb ,Cdb : depletion capacitances Cgd =W Cgd * , where Cgd * is the G-D fringing and overlap capacitance per unit gate length (parasitic) • MOSFET (operated sub-threshold; in forward active region; only valid for vbs = 0) ! gm = q ID n kT , go = " ID = ID VA Cgs =W L Cox # 1+ 2Cox #2 VGS $VFB( ) %SiqNA , Cdb : drain region depletion capacitance Cgd =W Cgd * , where Cgd * is the G-D fringing and overlap capacitance per unit gate length (parasitic) 7 Single transistor analog circuit building block stages Note: gl ≡ gsl + gel,; gl’ ≡ go + gl ! MOSFET Voltage gain, Av Current gain, Ai Input resistance, Ri Output resistance, Ro Common source " gm go + gl[ ] = "gmrl '( ) # # ro = 1 go $ % & ' ( ) Common gate * gm + gmb[ ] rl ' *1 * 1 gm + gmb[ ] * ro 1+ gm + gmb + go[ ] gt + , - . / 0 Source follower gm[ ] gm + go + gl[ ] *1 # # 1 gm + go + gl[ ] * 1 gm Source degeneracy (series feedback) * " rl RF # # * ro Shunt feedback " gm "GF[ ] go +GF[ ] * "gmRF " gl GF 1 GF 1" Av[ ] ro ||RF = 1 go +GF[ ] $ % & ' ( ) ! BIPOLAR Voltage gain, Av Current gain, Ai Input resistance, Ri Output resistance, Ro Common emitter " gm go + gl[ ] # "gmrl '( ) " $ gl go + gl[ ] r% ro = 1 go & ' ( ) * + Common base gm go + gl[ ] # gmrl '( ) #1 # r% $ +1[ ] # $ +1[ ]ro Emitter follower gm + g%[ ] gm + g% + go + gl[ ] #1 $ gl go + gl[ ] # $ r% + $ +1[ ]rl ' rt + r% $ +1[ ] Emitter degeneracy # " rl RF # $ # r% + $ +1[ ]RF # ro Shunt feedback " gm "GF[ ] go +GF[ ] # "gmRF " gl GF 1 g% +GF 1" Av[ ] ro ||RF = 1 go +GF & ' ( ) * + OCTC/SCTC Methods for Estimating Amplifier Bandwidth ! OCTC estimate of " HI : " HI # " i[ ] $1 i % & ' ( ) * + -1 = R i C i i % & ' ( ) * + -1 with Ri defined as the equivalent resistance in parallel with Ci with all other parasitic device capacitors (Cπ 's, Cµ's, Cgs 's, Cgd 's, etc.) open circuited. ! SCTC estimate of "LO: "LO # " j j $ = RjC j[ ] %1 j $ with Rj defined as the equivalent resistance in parallel with Cj with all other baising and coupling capacitors (CΙ 's, CO's, CE's, CS's, etc.) short circuited.