Understanding the Advantages and Properties of CMOS Logic Circuits - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download Understanding the Advantages and Properties of CMOS Logic Circuits - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Concept of effective width to length ratios For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased. For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased. . Parallel combination Series combination • At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications. • The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive. • Although the processing is more complicated for CMOS circuits than for NMOS circuits. • However, the advantages of CMOS digital circuits over NMOS circuits justify their use. CMOS: the most abundant devices on earth 2 Full rail-to-rail swing ⇒ high noise margins Logic levels not dependent upon the relative device sizes ⇒ transistors can be minimum size ⇒ ratio less Always a path to Vdd or GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒ large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input current No direct path steady-state between power and ground ⇒ no static power dissipation Propagation delay function of load capacitance and resistance of transistors CMOS properties 16.3.1:p-Channel MOSFET Revisited • In p-channel enhancement device. A negative gate-to- source voltage must be applied to create the inversion layer, or channel region, of holes that, “connect” the source and drain regions. • The threshold voltage VTP for p-channel enhancement load device is always negative and positive for depletion-mode PMOS. • Cross-section of p-channel enhancement mode MOSFET The operation of the p-channel is same as the n-channel device , except that the hole is the charge carrier, rather than the electron, and the conventional current direction and voltage polarities are reversed. Simplified cross section of a CMOS inverter • In the fabrication process, a separate p-well region is formed within the starting n-substrate. • The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n-substrate. 5 Biasing conditions for the CMOS inverter (cont.) • Case II: When both transistors are biased in the saturation region. iDN=iDP KN[VGSN-VTN]2=KP(VGSP+VTP)2 In terms of input output voltage we can write, KN[VI-VTN]2=KP(VDD-VI+VTP)2 The input voltage can be determine by simplifying above equation as, The above eq. can also be used to determine input voltage at the transition points. P N TN P N TPDD ItI K K V K KVV VV + ++ == 1 Both are in Saturation region CMOS inverter design consideration • The CMOS inverter usually design to have, (i)VTN =|VTP| (ii) K´n(W/L)=K´p (W/L) But K´n> K´p (because µn>µp) How equation (ii) can be satisfied? This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin. 8 Symmetrical properties of the CMOS inverter 6 CMOS inverter VTC VCC VCC Vin Vout kp=kn kp=5kn kp=0.2kn • Increase W of PMOS kp increases VTC moves to right • Increase W of NMOS kn increases VTC moves to left • For VTH = Vcc/2 kn = kp Wn ≈ 2Wp Effects of VIt adjustment • Result from changing kp/kn ratio: – Inverter threshold VIt ≠ Vcc/2 – Rise and fall delays unequal – Noise margins not equal • Reasons for changing inverter threshold – Want a faster delay for one type of transition (rise/fall) – Remove noise from input signal: increase one noise margin at expense of the other 7 CMOS inverter currents • When the output of a CMOS inverter is either at a logic 1 or 0, the current in the circuit is zero. • When the input voltage is in the range VTN<VI<VTP • Both transistors are conducting and a current exists in the inverter. 10 Dynamic Capacitive Power and energy stored in the PMOS device Case I: When the input is at logic 0: Under this condition the PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device. Power dissipation in the PMOS transistor is given by, PP=iLVSD= iL(VDD-VO) The current and output voltages are related by, iL=CLdvO/dt Similarly the energy dissipation in the PMOS device can be written as the output switches from low to high , Above equation showed the energy stored in the capacitor CL when the output is high. 2 2 0 2 0 0000 2 1 )0 2 ()0(, 2 ,)( DDLP DD LDDDDLP V O L V ODDLP O V OL V ODDLP O ODDLPP VCE VCVVCECVCE dCdVCEdt dt dVCPE DD DD DDDD = −−−=−= −=−== ∫∫∫∫ ∞∞ νν ννννν Power Dissipation and Total Energy Stored in the CMOS Device Case II: when the input is high and out put is low: During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as, The total energy dissipated during one switching cycle is, The power dissipated in terms pf frquency can be written as 2 2 1 DDLN VCE = 222 2 1 2 1 DDLDDLDDLNPT VCVCVCEEE =+=+= 2 DDLT T T VfCfEPt EPtPE ⇒=⇒=⇒= This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2 Dynamic capacitive power • Formula for dynamic power: • Observations – Does not (directly) depend on device sizes – Does not depend on switching delay – Applies to general CMOS gate in which: • Switched capacitances are lumped into CL • Output swings from Gnd to VDD • Input signal approximated as step function • Gate switches with frequency f fVCP DDLdyn 2= Dynamic short-circuit power • Short-circuit current flows from VDD to Gnd when both transistors are on saturation mode • Plot on VTC curve: VCC VCCVin Vout ID Imax Imax: depends on saturation current of devices 11 Inverter power consumption • Total power consumption fVCPtot IVf tt IVfVCP PPPP CCL leakCC fr CCCCLtot statscdyntot 2 max 2 ~ 2 +      + += ++= Power reduction • Reducing dynamic capacitive power: – Lower the voltage! • Quadratic effect on dynamic power – Reduce capacitance • Short interconnect lengths • Drive small gate load (small gates, small fan-out) – Reduce frequency • Lower clock frequency - • Lower signal activity fVCP DDLdyn 2= Power reduction • Reducing short-circuit current: – Fast rise/fall times on input signal – Reduce input capacitance – Insert small buffers to “clean up” slow input signals before sending to large gate • Reducing leakage current: – Small transistors (leakage proportional to width) – Lower voltage 12 Concept of Noise Margins NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input) NML=VIL-VOLU (noise margin for low input) NMH=VOHU - VIH (noise margin for high input) VI At point VIL the NMOS is biased in the saturation region and PMOS is biased in the nonsaturation region Taking derivative with respect to VI yields At VIL ⇒ Assume CMOS is symmetrical i. e. KN=KP ⇒ (1) (2) (3) (4) (5) Substituting (5) into (1) ⇒ (6) Noise Margins equations At point VIH the NMOS is biased in the nonsaturation region and PMOS is biased in the saturation region Taking derivative with respect to VI yields (6) (9) (8) (7) Assume CMOS is symmetrical i. e. KN=KP (10) Substituting (10) into (6) ⇒ Noise Margins equations (cont.) Summary of the noise margin of a symmetrical CMOS inverter NML = VIL - VOLU (noise margin for low input) NMH = VOHU - VIH (noise margin for high input) 15 Fan-In and Fan-Out • The Fan-in of a gate is the number of its inputs. Thus a four input NOR gate has a fan-In of 4. • Similarly, Fan-Out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications. Switching Time and Propagation Delay Time • The dynamic performance of a logic circuit family is characterized by propagation delay of its basic inverter. The propagation delay time is define as the average of low-to-high propagation delay time and the high-to-low propagation delay time. • The propagation delay time is directly proportional to the switching time and increases as the Fan-out increases. Therefore, the maximum Fan-out is limited by the maximum acceptable propagation delay time. Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates. Transmission Gates • Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another. 16 NMOS transmission gate as an open switch. • The figure shows NMOS transmission gate. The transistor in the gate can conduct current in either direction. The bias applied to the transistor determines which terminal acts as the drain and which terminal acts as the source. When gate voltage φ=0 The n-channel transistor is cut off and the transistor acts as an open switch Characteristics of NMOS transmission gate (at high input) If φ=VDD, VI=VDD, and initially, the output V0 is 0 and capacitance CL is fully discharged. Under these conditions, the terminal ‘a ‘acts as the drain because its bias is VDD, and terminal ‘b’ acts as the source because its bias is 0. The gate to source voltage can be written as VGS=φ-VO or VGS= VDD-VO As CL charges up and Vo increases, the gate to source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero. This implies that the VO=VO(max) when VGS=VTN Or VO(max) = VDD-VTN d S G This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN. This is one of the disadvantage of an NMOS transmission gate when VI=high Characteristics of NMOS transmission gate (at low input) • When VI=0 and φ=VDD and VO=VDD-VTN at t=o (initially). It is to be noted that in the present case terminal b acts as the drain and terminal a acts as the source. Under these conditions the gate to source voltage is, VGS=φ-VI VGS=VDD-o vGS-vDD This implies that value of VGS is constant. In this case the capacitor is fully discharge to zero as the drain current goes to zero. VO=0 This implies that the NMOS transistor provide a “good” logic 0 when VI=low VDD-Vt G S D source drain gate Why NMOS transmission gate does not remain in a static condition? • The reverse leakage current due to reverse bias between terminal b and ground begins to discharge the capacitor, and the circuit does not remain in a static condition. VDD-Vt source drain gate Exampte 16.13 objective: Estimate the rate at which the output voltage ¥g in Figure 16.57 decreases with time, Assume the capacitor is initially charged lo vp = 4. Let C, = 1 pP and assurae the reverse-biased pm junction leakage current is a constant at é; = nA. Soluan: ‘The voltage acrovs the capacitor can be written as db fu where the minus sign indicates tha: the current is leaving the positive terminal of the capacitor. Since i, is a constant, we have vox ett K p= et where K, = vo(t = 0) = 4V is the initial condition. Therefore, *o c. ‘The rute at which the output volcage decreases is, doe <> -1V/m8 So -E ape Ws 1 vA I ‘Therefore, in this cxample, the capacitor would completely dischaege in 4s. Comment: Even though the NMOS transmission gate may introduce a dynamic con+ dition into a circuit, this gate ia still useful in clocked logic citenits in which a clock signal is periodically applied to the NMOS transistor gate. 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As VO1 goes high, VO2 goes low. If φ2 is high low will transmitted through MN2 and VO4 would be at logic 1. Thus logic 1 shifted from input to output. In shift register the input signal is transmitted, or shifted, from the input to the output during one clock cycle. Dynamic Shift Registers at various times Suppose VDD=5V and VTN=1V. At t=t1 , V1=φ1=5V, vO2 goes low At this time MN2 is still in cutoff (φ2=0) even though input of MN2 has been changed. This implies that vO3 and vO4 depend on the previous history. Similarly at t=t3, φ2 is high, and logic 0 at vO2 is transmitted to vO3, which force vO4 to 5V. Thus the input information is transmitted to output during one clock cycle. Transparent mode Hold mode Dynamic Shift Registers at Various Times (cont.) • Consider when t=t4, vI=0, and φ1=5V, so VO1=0 and VO2=5V.Vo3 and Vo4 depend on previous history • At t=t5, φ2=5V, vO3 charges to VDD- VTN=4V and VO4 goes low. • Thus logic 0 is shifted (transmitted) from input to output. • Also note that vO3 and vO4 are depend on previous history of their inputs instead of current inputs (they are having memory). NMOS shift register is also dynamic (why?) • The output charged capacitor does not remain constant with time because it is discharge through the transmission gate transistor. • In order to prevent logic errors, the clock signal period T must be small compared to effective RC discharge time constant. For example at t = t2, VO1=4V, φ1=0 and MN1 is cutoff.VO1 will start to to decay and VO2 will begin to increase. 21 CMOS Dynamic Shift Registers • The operation of the CMOS shift register is similar to the NMOS register except for the voltage levels. • For example, when vI=φ1=VDD. Then vO1=VDD and vO2=0. when φ2 goes high, then vo3 switch to zero, vo4=vDD. • Thus input signal is shifted to the output during one clock cycle. NMOS R-S Flip Flop • Flip- flops are bistable circuits usually formed by cross-coupling two NOR gates. The output of the two NOR circuits are connected back to the inputs of the opposite NOR gates. When S=logic 1 and R=logic 0 =logic 0 and Q=logic 1=VDD Transistor M2 is then also biased in conducting state. If S returns to logic 0, nothing in the circuit can force a change and flip flop stores the previous logic states, although M1 turned off (but M2 remains tuned on). Q NMOS R-S Flip Flop (cont.) • When R=logic 1 and S=logic 0 • Then M4 turn on so output goes low. With S=Q=Logic 0, both M1 and M2 are cutoff and goes high. The flip-flop is now in reset state. • If both S and R inputs go high. Then both outputs Q and would go low, which implies that output is not complementary. This condition is forbidden or nonallowed condition. Q 22 CMOS R-S Flip-Flop • The operation sequence of CMOS R-S flip flop is same as NMOS. • For example: If S = logic 1 and R = logic 0, then MN1, is turned on, Mp1, is cut off, and goes low. • With = R = logic 0, then both MN3 and MN4 are cut off, both MP3 and Mp4 are biased in a conducting state so that the output Q goes high. • With Q = logic 1, MN2 is biased on, Mp2 is biased off, and the flip-flop is in a set condition. • When S goes low, MN1, turns off, but MN2 remains conducting, so the state of the flip-flop does not change. • Q Q CMOS R-S Flip-Flop (cont.) • When S = logic 0 and R = logic 1, then output Q is forced low, output goes high, and the flip-flop is in a reset condition. • Again, a logic 1 at both S and R is considered to be a forbidden or a nonallowed condition, since the resulting outputs are not complementary. Q Static vs Dynamic Storage • Static storage –preserve state as long as the power is on –have positive feedback (regeneration) with an internal connection between the output and the input –useful when updates are infrequent (clock gating) • Dynamic storage –store state on parasitic capacitors –only hold state for short periods of time (milliseconds) – require periodic refresh –usually simpler, so higher speed and lower power Static D-type Flip-Flop • A D-type flip-flop is used to provide a delay. The logic bit on the D input is transferred to the output at the next clock pulse. When the CMOS transmission gate turn off (φ=0), the pn junction in the MN1 transmission gate transistor is reverse biased.