Download Combinational Logic Circuits-Introduction to Microelectronic Circuits-Lecture 29 Slides-Electrical Engineering and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 29, Slide 1EECS40, Fall 2003 Prof. King Lecture #29 ANNOUNCEMENTS • Lab project: – Bring a check ($50, payable to “UC Regents”) to lab this week in order to receive your Tutebot kit. (You will receive this back, when you return the kit.) – Extra credit will be awarded if you endow your Tutebot with additional “intelligence”! • Prof. King’s office hour tomorrow (11/6) is cancelled OUTLINE – Synthesis of logic circuits – Minimization of logic circuits Reading: Schwarz & Oldham pp. 403-411 Lecture 29, Slide 2EECS40, Fall 2003 Prof. King Combinational Logic Circuits • Logic gates combine several logic-variable inputs to produce a logic-variable output. • Combinational logic circuits are “memoryless” because their output value at a given instant depends only on the input values at that instant. • Next time, we will study sequential logic circuits that possess memory because their present output value depends on previous as well as present input values. 2 Lecture 29, Slide 3EECS40, Fall 2003 Prof. King Boolean Algebra Relations A•A = A A•A = 0 A•1 = A A•0 = 0 A•B = B•A A•(B•C) = (A•B)•C A+A = A A+A = 1 A+1 = 1 A+0 = A A+B = B+A A+(B+C) = (A+B)+C A•(B+C) = A•B + A•C A•B = A + B A•B = A + B De Morgan’s laws Lecture 29, Slide 4EECS40, Fall 2003 Prof. King Boolean Expression Example F = A•B•C + A•B•C + (C+D)•(D+E) F = C•(A+D+E) + D•E 5 Lecture 29, Slide 9EECS40, Fall 2003 Prof. King NAND Gate Implementation • De Morgan’s law tells us that is the same as • By definition, is the same as All sum-of-products expressions can be implemented with only NAND gates. Lecture 29, Slide 10EECS40, Fall 2003 Prof. King Creating a Better Circuit What makes a digital circuit better? • Fewer number of gates • Fewer inputs on each gate – multi-input gates are slower • Let’s see how we can simplify the sum-of- products expression for S1, to make a better circuit… – Use the Boolean algebra relations 6 Lecture 29, Slide 11EECS40, Fall 2003 Prof. King Karnaugh Maps • Graphical approach to minimizing the number of terms in a logic expression: 1. Map the truth table into a Karnaugh map (see below) 2. For each 1, circle the biggest block that includes that 1 3. Write the product that corresponds to that block. 4. Sum all of the products A B 2-variable Karnaugh Map 0 1 1 0 A 1 0 BC 00 01 11 10 3-variable Karnaugh Map 4-variable Karnaugh Map CD 00 01 11 10 AB 00 01 11 10 Lecture 29, Slide 12EECS40, Fall 2003 Prof. King 01110 10001 01101 01011 1 0 0 0 S1 1 0 1 0 C 1 0 0 0 A 1 1 0 0 B 1 1 1 0 S0 Input Output 11101 01000 10110100 A BC BC AC AC AB S1 = AB + BC + AC Simplification of expression for S1: Karnaugh Map Example
