Combinational MOS Logic Circuits - Lecture slides | EE 534, Study notes of Electrical and Electronics Engineering

Download Combinational MOS Logic Circuits - Lecture slides | EE 534 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE534 VLSI Design System Summer 2003 Lecture 9:Chapter 7 Combinational MOS logic circuits Impact of CL on Psc: slop engineering Vin Vout CL Isc ≈ 0 Vin Vout CL Isc ≈ Imax Large capacitive load Output fall time significantly larger than input rise time. Small capacitive load Output fall time substantially smaller than the input rise time. Review: CMOS inverter static power Static power consumption: Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD+VTP Leakage current: determined by “off” transistor Influenced by transistor width, supply voltage, transistor threshold voltages VDD VI<VTN Ileak,n Vcc VDD Ileak,p Vo(low) VDD Review: Dynamic Power Consumption Vin Vout CL Vdd Review: Short Circuit Power Consumption Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. Vin Vout CL Isc Review: CMOS inverter power dissipation P = CL VDD2 f + tscVDD Ipeak + VDD Ileakage Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) Leakage power (~2% today and increasing) Combinational vs. Sequential Logic Output = f(In) Output = f(In, Previous In) Static vs. Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of N requires 2N devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only N + 2 transistors takes a sequence of precharge and conditional evaluation phases to realize logic functions