Combinational MOS Logic Circuits - Lecture Slides | EE 534, Study notes of Electrical and Electronics Engineering

Download Combinational MOS Logic Circuits - Lecture Slides | EE 534 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE 534 fall 2003 University of South Alabama EE534 VLSI Design System Fall 2003 Lecture 14:Chapter 7 Combinational MOS logic circuits EE 534 fall 2003 University of South Alabama Review: Energy & Power Equations E = CL VDD2 P0→1 + tsc VDD Ipeak P0→1 + VDD Ileakage P = CL VDD2 f0→1 + tscVDD Ipeak f0→1 + VDD Ileakage f0→1 = P0→1 * fclock Leakage power (~2% today and increasing) Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) EE 534 fall 2003 University of South Alabama CMOS Logic Circuits 7 Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits. EE 534 fall 2003 University of South Alabama Static complimentary CMOS Complementary pullup network (PUN) and pulldown network (PDN) Only one network is on at a time PUN: PMOS devices PDN: NMOS devices PUN and PDN are dual networks Output is always connected to Vcc or Gnd PUN A B C PDN A B C F Why NMOS should be used as a pull-down and pMOS should be used a pull-up device? EE 534 fall 2003 University of South Alabama Threshold Drops VDD VDD →PDN 0 → CL CL PUN VDD VDD 0 → CL VDD → VDD CL EE 534 fall 2003 University of South Alabama CMOS NAND 011 101 110 100 FBA A B A • B A B A B EE 534 fall 2003 University of South Alabama CMOS NOR A + B A B 011 001 010 100 FBA A B A B EE 534 fall 2003 University of South Alabama Complex CMOS Gate OUT = !(D + A • (B + C)) A D B C EE 534 fall 2003 University of South Alabama VTC is Data-Dependent F= A • B M1 M2 M3 M4 0 1 2 3 0 1 2 A,B: 0 -> 1 B=1, A:0 -> 1 A=1, B:0->1 0.5µ/0.25µ NMOS 0.75µ /0.25µ PMOS The threshold voltage of M2 is higher than M1 due to the body effect (γ) VTn2 = VTn0 + γ(√(|2φF| + Vint) - √|2φF|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint VTn1 = VTn0 D D S S weaker PUN A B A VGS2 = VA –VDS1 Cint B VGS1 = VB EE 534 fall 2003 University of South Alabama Concept of effective width to length ratios Series combinationParallel combination For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased. . For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased. EE 534 fall 2003 University of South Alabama Analysis of CMOS gates Represent “on” transistors as resistors 1 1 W R W R 1 W R • Transistors in series → resistances in series • Effective resistance = 2R • Effective width = ½ W EE 534 fall 2003 University of South Alabama Static CMOS Logic Characteristics For VTH, the VTH of the equivalent inverter is used (assumes all inputs are tied together) For specific input patterns, VTH will be different For VIL and VIH, only the worst case is interesting since circuits must be designed for worst-case noise margin For delays, both the maximum and minimum must be accounted for in race analysis EE 534 fall 2003 University of South Alabama Equivalent Inverter: VTH Example: NAND gate threshold VTH Three possibilities: A & B switch together A switches alone B switches alone What is equivalent inverter for each case? EE 534 fall 2003 University of South Alabama CMOS NAND gate and its inverter equivalent Can we estimate switching threshold of the NAND gate by using CMOS inverter expression for the switching threshold? n p pTDD n p nT th K K VV k k V INRV + −+ = 1 )( )( ,, If Kn=Kp, Vth=? WN WN WP WP n p pTDD p p nT th K K VV k k V NANDV 4 1 )( 4 )( ,, + −+ = 2WP 2KP ½ WN Kn/2