Combinational System Analysis - Lecture Slides | EE 260, Study notes of Microelectronic Circuits

Download Combinational System Analysis - Lecture Slides | EE 260 and more Study notes Microelectronic Circuits in PDF only on Docsity! CEG/EE 260 Digital Computer Hardware Dr. Travis Doom, Associate Professor Department of Computer Science and Engineering Wright State University Section I: Combinational System Analysis CEG/EE 260 - 2 Acknowledgements These slides were developed with the aid of examples found in: – “Digital Design” – Frank Vahid – “Logic and Computer Design Fundamentals” - M. Morris Mano – “Digital Design: Principles and Practices” - John Wakerly – “Introduction to Computing Systems” – Patt/Patel Figures many of the slides were kindly provided by: – Dr. Roger L. Haggard – Dr. Travis E. Doom CEG/EE 260 - 3 What is a computer? What is computation? There are many sorts of computing devices, they fall into two categories: – Analog: machines that produce an answer that measures some continuous physical property such as distance, light intensity, or voltage. Examples? – Digital: machines that perform computations by manipulating a fixed finite set of elements. Examples? – The difficulty with analog devices is that it is very hard to increase their accuracy. Before modern digital computers, the most common digital machines were adding machines. – Adding machines perform exactly one sort of operation. Computers also perform one operation… but their operation is to accept a set of instructions that tell it how to do any sort of computation. CEG/EE 260 - 4 Universal computing devices Turing’s Thesis: Computer scientists believe that ANYTHING that can be computed, can be computed by a computer (provided that it has enough time and enough memory). What does this imply? – All computers (from the least expensive to the most expensive) are capable of computing EXACTLY the same things IF they are given enough time and enough memory. – Some computers can do things faster, but none can do more than any other computer. – All computers can do exactly the same same things! Thus, any given problem is either computable or it is not computable – Problems may be computable, but still not feasible (NPC) CEG/EE 260 - 5 How do we get the electrons to do the work? We describe our problems in English or some other natural language. Computer problems are solved by electrons flowing around inside the computer. It is necessary to transform our problem from a natural language to the voltages that influence the flow of electrons. This transformation is really a sequence of systematic transformations, developed and improved over the last 50 years, which combine to give the computer the ability to carry out what may appear to be very complicated tasks. In reality, these tasks must be simple and straight-forward. CEG/EE 260 - 6 The principle of design abstraction General model for Engineering (Byrne, 1992) Existing System Target System Implementation Design Requirements Requirements Con- ceptual Con- ceptual Design Implementation re-think re-specify re-design re-build Alteration Reverse Engineering Abstraction Forward Engineering Refinement CEG/EE 260 - 7 Levels of abstraction in digital computation Design Process Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices Software level Hardware level Logic level Computer Science Computer Engineering Computer/Elect. Engineering CEG/EE 260 - 8 The statement of the problem We describe problems that we wish to solve with a computer in a “natural language.” Natural languages are fraught with a lot of things unacceptable for providing instructions to a computer. The most important of these unacceptable attributes is ambiguity. To infer the meaning of a sentence, a listener is often helped by context that the computer does not have. Example: “Time flies like an arrow.” – How fast time passes – Track meet – Gossip A computer is an electronic idiot and can not deal with any ambiguity, thus… Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices CEG/EE 260 - 9 The algorithm The first step in the sequence of transformations is to transform the natural language description of the problem to an algorithm. An algorithm is a step-by-step procedure: – That transforms an input (possibly NULL) into some output (or output action) – That is guaranteed to terminate Definiteness: Each step is precisely stated. Effective computability: Each step must be something the computer can perform Finiteness: The procedure must terminate For any computable problem, there are an infinite number of algorithms to solve it. – Which solution is best? Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices CEG/EE 260 - 10 The programming language The next step is to transform the algorithm into a computer program Programming languages are unambiguous “mechanical” languages There are two kinds of programming languages: – High-level languages are machine independent. They are “far above” the (underlying) computer – Low-level languages are machine dependent. They are tied to the computer on which the program will execute. There is generally only one such language per machine (referred to as its ASSEMBLY language). Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices CEG/EE 260 - 11 The instruction set architecture (ISA) The next step is to translate the program into the instruction set of the particular computer that will be used to carry out the work of the program. The Instruction Set Architecture (ISA) is the complete specification of the interface between programs that have been written and the underlying hardware that must carry out the work of those programs. – Examples: IA-32 (Intel, AMD, and others), PowerPC (Motorola) Programs are translated from high languages in to the ISA of the computer on which they will be run by a program called a compiler (specific to the ISA). Programs are translated from assembly to the ISA by an assembler Analogy: A car – The car’s ISA describes what the driver sees/uses. Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices CEG/EE 260 - 12 The microarchitecture The next step is to transform the ISA into an implementation. The detailed organization of an implementation is called its microarchitecture. – The IA-32 has been implemented by several different processors over the past twenty years 8086 (Intel, 1979), 8286, 8386, 8486, Pentium, PentiumII, Athlon, PentiumIII. – Each implementation is an opportunity for computer designers to make different trade-offs between cost and performance. [Computer design is always an exercise in trade-offs.] Analogy: A car – The implementation of a car’s ISA is what goes on under the hood. Here all automobiles makes and models are different. Some with fuel injection, some have eight cylinders, some are turbocharged… in each case the “microarchitecture” of a specific automobile is the result of the automobile designers’ decisions regarding cost and performance. Algorithm & Language The Problem ISA & Microarchitecture Circuits & Devices CEG/EE 260 - 25 Electronic Aspects of Digital Design Digital devices are built with analog components A range of voltages associated with each logic value ( 0 or 1 ) Noise margin : The difference between the range boundaries – in low state = VILmax - VOLmax = 1.5 V - 0.1 V= 1.4 V for 5V CMOS – in high state = VOHmin - VIHLmin = 4.9 V - 3.5 V= 1.4 V for 5V CMOS Voltage Outputs Noise Margin Inputs Logic 0 Logic 0 Logic 1 Logic 1 Invalid CEG/EE 260 - 26 Electronic Aspects of Digital Design Logic gates Specifications : - Conditions under which the digital device produces and recognizes logic signals within the appropriate range. - Examples : - Power-supply voltage - Temperature - Loading - Frequency Manufacturer specifications ( data sheets ) CEG/EE 260 - 27 Propagation Delay The delay time between input transitions and the output transitions due to the propagation delay of the the logic gates. tp of a signal depends on the signal path inside the logic circuit For a logic gate tpLH may not equal tpHL tp is specified in the manufacturer data sheets of the IC’s Example : -The time delay for 74x00 in nanoseconds for three logic Families: Typical Maximum tpLH tpHL tpLH tpHL 74LS00 9 10 15 15 74HCT00 11 11 35 35 74ACT00 5.5 4.0 9.5 8.0 To find tp for a signal, add the propagation delays of all gates along the path of the signal CEG/EE 260 - 28 Timing Diagrams Y X X Y tpLH(XY) tpHL(XY) trise tfall Actual Timing Diagram Functional Timing Diagram X Y Functional timing diagrams do not show exact delays. “lining up” everything allows the diagram to display more clearly which functions are performed in response to which action – Illustrates operation, but does not specify upper and lower limits – Not always sufficient for a real design CEG/EE 260 Digital Computer Hardware Dr. Travis Doom, Associate Professor Department of Computer Science and Engineering Wright State University Section III: Complex Combinational Systems CEG/EE 260 - 30 Decoder Multiple-input/multiple-output device. Decoder - Inputs (n) < outputs (m). Encoder - Inputs (n) > outputs (m) Converts input code words into output code words. One-to-One mapping : - Each input code produces only one output code. Input codes : - Binary Code - Gray Code - BCD Code - Your Code ! input code enable inputs output codeDECODER input code output code ENCODER CEG/EE 260 - 31 Binary Decoder n-to-2^n decoder: n inputs and 2^n outputs. Input code : Binary Code. Output code : 1-out-of-2^n , One output is asserted for each input code. Example : n=2, 2-to-4 decoder Inputs Outputs EN I1 I0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 EN I0 I1 Y0 Y1 Y2 Y3 CEG/EE 260 - 32 Comparators Compares Two binary words and indicate if they are equal Advanced Comparators : 1-bit Comparator : XOR gate , the Output is 1 if A<>B A Comparator OUTPUT B A Comparator A=B B A>B A<B A B F CEG/EE 260 - 33 Iterative Combinational Logic Iterative logic array: A device consisting of identical sub-circuits connected together in a chain to perform a larger overall function Iterative Comparator : cascaded 1-bit comparators 1-bit comparator : Function Table EQI X Y EQO 0 x x 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 X Y EQI EQO X Y EQI EQO X0 Y0 EQ0 =1 EQ1 X Y EQI EQO X1 Y1 EQ1 X Y EQI EQO X(N-1) Y(N-1) EQNEQ1(N-1) CEG/EE 260 - 34 Multiplexers Multiplexing: transmitting large number of signals over a small number of channels or lines Digital multiplexer (MUX): selects one of many input lines and directs it to a single output (often a bus or “party line”). Selection lines controls the selection of a particular input m-bit 2n x 1 multiplexer: – n selection lines, 2n m-bit inputs, 1 m-bit output. Example : 4-to-1 line multiplexer: Function Table : S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 4 1× MUX I0 Y S1 S0 Inputs Output Select I1 I2 I3 CEG/EE 260 - 35 Implementing Logic Functions Any n-variable logic function can be implemented using a 2n-to-1 MUX – (In fact, MUXs are a universal device! Any combinational function can be implemented using only MUXes). The inputs variables are connected to the select input. The function value for each input combination (0 or 1) is connected to the corresponding input of the MUX Example: Row X Y F 0 0 0 0 1 0 1 1 2 1 0 0 3 1 1 1 4 1× MUX I0 Y S1 S0 FI1 I2 I3 X Y 0 1 0 1 CEG/EE 260 - 36 Functional Decomposition Effective way for using MUX to implement Logic Functions. n-variable truth table can be simplified using any MUX : – Use one or more variables as control inputs – Decompose the remaining logic function in terms of the remaining inputs – For 3-variable Logic Function , the decomposed truth table is : Row X Y Z F 0,1 0 0 x F00(Z) 2,3 0 1 x F01(Z) 4,5 1 0 x F10(Z) 6,7 1 1 x F11(Z) Values of Fxx(Z) = 0 or 1 or Z or Z’ 4 1× MUX I0 Y S1 S0 FI1 I2 I3 X Y F00(Z) F01(Z) F10(Z) F11(Z) CEG/EE 260 - 37 Demultiplexers Demultiplexer (DMUX) performs the opposite function of a MUX. A digital Demultiplexer receives input data on a single input and transmits it on one of 2^n possible outputs according to the value of the n select inputs MUX/DMUX are used in data transmission Source Destination MUX DMUX A B C A B C Select Select BUS CEG/EE 260 - 38 Programmable Logic Devices PLDs are generic logic devices capable of implementing a wide range of combinational (and sequential) functions. – O0 = F0(x0…xn) – O1 = F1(x0…xn) – … – Om = Fm(x0…xn) Combinational PLD m outputsn inputs CEG/EE 260 - 39 Why do Computers use Base 2? Base 10 Number Representation – Natural representation for human transactions Floating point number cannot exactly represent $1.20 – Even carries through in scientific notation 1.5213 X 104 Hard to Implement Electronically – Hard to store ENIAC (First electronic computer) used 10 vacuum tubes / digit – Hard to transmit Need high precision to encode 10 signal levels on single wire – Messy to implement digital logic functions Addition, multiplication, etc. Base 2 Number Representation – Easy to store with bistable elements – Reliably transmitted on noisy and inaccurate wires Examples – Represent 1521310 as 111011011011012 – Represent 1.2010 as 1.0011001100110011[0011]…2 – Represent 1.5213 X 104 as 1.11011011011012 X 213 1.20 = 1x10^0 + 2x10^-1 + 0x10^-2 1.20 = 1x2^0 + 0x2^-1 + 0x2^-2 +… CEG/EE 260 - 40 Unsigned Binary Integers 00000100001001004 00000011000110113 00000010000100102 00000001000010011 00000000000000000 8-bits5-bits3-bits Y = “abc” = a.22 + b.21 + c.20 N = number of bits Range is: 0 ≤ i < 2N – 1 Umin = 0 Umax = 2N – 1 (where the digits a, b, c can each take on the values of 0 or 1 only) Problem: • How do we represent negative numbers? CEG/EE 260 - 41 Signed Magnitude Leading bit is the sign bit 00100+4 10100-4 10011-3 10010-2 00011+3 00010+2 00001+1 00000+0 10000-0 10001-1 Range is: -2N-1 + 1 < i < 2N-1 – 1 Smin = -2N-1 + 1 Smax = 2N-1 – 1 Y = “abc” = (-1)a (b.21 + c.20) Problems: • How do we do addition/subtraction? • We have two numbers for zero (+/-)! CEG/EE 260 - 42 Two’s Complement Transformation – To transform a into -a, invert all bits in a and add 1 to the result 10000-16 …… 01111+15 …… 00011 00010 00001 00000 11111 11110 11101-3 -2 +3 +2 +1 0 -1 Range is: -2N-1 < i < 2N-1 – 1 Tmin = -2N-1 Tmax = 2N-1 – 1 Advantages: • Operations need not check the sign • Only one representation for zero • Efficient use of all the bits CEG/EE 260 - 55 Types of Sequential Logic An Asynchronous Sequential Circuit uses ordinary gates and feedback loops to implement “memory” in a logic circuit. – Meeting minimum pulse width requirements may be tricky A Synchronous Sequential Circuit uses flip-flops (internally, an asynchronous sequential device) to form useful sequential logic functions or applications. – The state variables and outputs of a synchronous system change with respect to a controlling clock signal – Meeting minimum pulse width requirements is simplified by restating all timing constraints in terms of the clock signal CEG/EE 260 - 56 Period tH tL State change Active High Period tH tL State change Active Low Duty Cycle = tL/Period Frequency = 1/Period Clock Characteristics Duty Cycle = tH/Period CEG/EE 260 - 57 Sequential Logic Definitions Clock - the master timing element behind the state changes of most sequential circuits. – a clock signal is active high if the state changes occur at the rising edge (for edge triggered devices) or in the logic 1 state (for pulse-triggered devices) – active low if state changes occur at the falling edge or in the logic 0 state. Clock Period - time between successive transitions in the same direction Clock Frequency - reciprocal of the clock period Clock Tick - the first edge or pulse in a clock period, or the period itself Duty Cycle - the percentage of time that a clock is at its assertion level CEG/EE 260 - 58 Positive-Edge-Triggered D Flip-Flop D >CLK Q Q D C Q D C Q Q D CLK Q /Q D CLK Q /Q 0 1 X X 0 1 0 1 Last Q Last Q 1 0 Last /Q Last /Q Master SlaveQM Device samples inputs and changes state only on a clock edge. Simplifies the meeting of setup/hold times. Master FF - transparent on CLK’ (entire pulse) Slave FF - transparent on CLK (master fixed) CEG/EE 260 - 59 MSI Quad/Hex Registers CLK CLR 4Q 4Q 3Q 3Q 2Q 2Q 1Q 1Q 74LS175 1D 2D 3D 4D CLK CLR 6Q 5Q 4Q 3Q 2Q 1Q 74LS174 1D 2D 3D 4D 5D 6D D 1Q CLR Q Q /1Q 1D D 2Q CLR Q Q /2Q 2D D 3Q CLR Q Q /3Q 3D D 4Q CLR Q Q /4Q 4D CLK /CLR 74LS175 All four flip-flops use the same clock! CEG/EE 260 - 60 Octal Register with Parallel Load Enable CLK Load 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q D Q 1D /Load CLK 1Q Why don’t we gate the clock? 1b-mux CEG/EE 260 - 61 Clocked Synchronous State-machine Model Next-state Logic F State Memory clock Output Logic G excitation inputs clock current state outputs (Mealy machine) Moore Machine State memory: Usually edge-triggered D or JK flip-flops CEG/EE 260 - 62 Timing Diagram CLOCK flip-flop outputs tH tL tclk tffpd combinational logic excitation inputs tcomb setup-time margin tsetup thold CEG/EE 260 - 63 Programmable Logic Definitions Digital integrated circuit (MSI, LSI, VLSI) – manufactured as a standard off-the-shelf component – containing “regular” array of logic gates and flip-flops – whose logic functions are determined by the application design engineer and implemented locally Many types of programmable logic – sometimes generically called PLDs (Programmable Logic Devices) – PAL or PLD – PROM – FPGA output input Combinational PLD CEG/EE 260 - 64 Programmable Logic Definitions PLA – Programmable Logic Array – first PLDs – simple programmable AND/OR array – programmed by “blowing fuses” by hand or by mask CEG/EE 260 - 65 PAL – Programmable Array Logic – similar to a PLA, but the OR- array is fixed – most commonly used PLD – may include input/output flip- flops GAL – Generic Array Logic – can be configured to emulate the AND/OR, flip-flop, and output structure of a variety of combinational and sequential PAL devices FPGA – Field Programmable Gate Array Programmable Logic CEG/EE 260 - 66 Read-Only Memory (ROM) A combinational circuit with n inputs and b outputs: 2n x b ROM Address inputs A(n-1, ... , 0) n b Data outputs D(b-1, ... , 0) Programmable ⎯ values determined by user Nonvolatile ⎯ contents retained without power Uniform (Random) Access ⎯ delay is uniform for all addresses CEG/EE 260 - 67 Read-Only Memory (ROM) Two views: – ROM stores 2n words of b bits each, or – ROM stores an n-input, b-output truth table Example: A1 A0 D3 D2 D1 D0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Stores 4 4-bit words, or stores 4 functions of 2 input variables b = 4n = 2 CEG/EE 260 - 68 Using ROMs for Combinational Logic A 3-input, 4-output combinational logic function: Function: 2-to-4 Decoder with Polarity Control A2 = Polarity (0 = active Low, 1= active High) A1, A0 = I1, I0 (2-bit input ) D3...D0 = Y3...Y0 (4-bit decoded output) Inputs Outputs A2 A1 A0 D3 D2 D1 D0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 8 × 4 ROM A0 D0 A1 D1 A2 D2 D3 Y0 I1 POL Y1 Y2 Y3 I0 CEG/EE 260 - 69 Internal Structure of 4×4 Diode ROM D0 D1 D2 D3 2 to 4 Decoder A1 A0 Bit Lines /w0 /w1 /w2 /w3 Diode 1 No Diode 0 0101 0001 1000 1111 1 of n Word Lines R0R1R2R3 +5 V Why use diodes? Why not replace them with wires? CEG/EE 260 - 70 Types Of ROMs (1) Mask ROM – Connections made by the semiconductor vendor – Expensive setup cost – Several weeks for delivery – High volume only – Bipolar or MOS technology PROM – Programmable ROM – Connections made by equipment manufacturer – Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses – Bipolar technology – One-time programmable Word Line Bit Line CEG/EE 260 - 71 Internal Structure of Transistor ROM R0R1R2R3 +5 V /D3 /D2 /D1 /D0 Transistor 1 No transistor 0 w3 Replace diodes with MOS transistors Change decoder to active-high outputs 1000 CEG/EE 260 - 72 EPROM and EEPROM Structure VDD Floating gate Nonfloating gate Active-high word lines Active-low bit lines CEG/EE 260 - 85 Machine Words Machine Has “Word Size” – Nominal size of integer-valued data Including addresses – Most current machines are 32 bits (4 bytes) Limits addresses to 4GB Becoming too small for memory- intensive applications – High-end systems are 64 bits (8 bytes) Potentially address ≈ 1.8 X 1019 bytes – Machines support multiple data formats Fractions or multiples of word size Always integral number of bytes Sizes of C Objects (in Bytes) C Data Type Typical 32-bit – Int 4 – long int 4 – char 1 – short 2 – float 4 – double 8 – long double 8 – char * 4 – Or any other pointer CEG/EE 260 - 86 Byte-Oriented Memory Organization Programs Refer to Virtual Addresses – Conceptually very large array of bytes – Actually implemented with hierarchy of different memory types SRAM, DRAM, disk Only allocate for regions actually used by program – In Unix and Windows NT, address space private to particular “process” Program being executed Program can clobber its own data, but not that of others Compiler + Run-Time System Control Allocation – Where different program objects should be stored – Multiple mechanisms: static, stack, and heap – In any case, all allocation within single virtual address space CEG/EE 260 - 87 The von Neumann Model - Memory We will access memory via a standard interface – The Memory Address Register sets up the decoder circuitry in the memory – The Memory Data Register hold contents to/from memory – The Write enable signal indicates which direction information should flow. Memory Read – Read: the contents of the specified address will be written to the Memory Data Register. – If: Write enable is not applied in any given clock tick – Then: MDR ← M[(MAR)] Memory Write – Write: the value to be stored is first written to the Memory Data Register, then the Write Enable is asserted, and the contents of the MDR are written to the specified address. – If: a Write enable is applied is any given clock tick – Then: M[(MAR)] ← MDR CEG/EE 260 - 88 The von Neumann Model - CPU Processing Unit - Does the actual work! – Can consist of many units, each specializing in one complex function. – At a minimum, has Arithmetic & Logic Unit (ALU) and temporary storage (registers). – The number of bits a basic Processing Unit operation can handle is called the WORD SIZE of the machine. – ALU Performs basic operations: add, subtract, and, not, etc. Generally operates on whole words of data. Some can also operate on subsets of words (eg. single bits or bytes). – Registers: Fast “on-board” storage for a small number of words. Invaluable for intermediate data storage while processing. Close to the ALU (much faster access than RAM). General Purpose Registers (GPRs) are available to the programmer. CEG/EE 260 - 89 The von Neumann Model – Control Unit and I/O Control Unit – The control unit coordinates all actions needed to execute the instruction It fetches & decodes each instruction, and sets up the appropriate inputs for the Memory, Processing, and I/O units as required. It communicates with memory via the Program Counter (PC) and Instruction Register (IR) – PC (aka Instruction Pointer) Holds the address of the next instruction to be fetched. – IR Holds the instruction currently being executed. This can be a single word, or multiple words. Input & Output – Generically known as peripherals - they are external to the CPU. – This means we will have to develop mechanisms for autonomous devices to communicate with each other - more on this later. CEG/EE 260 - 90 Instruction Cycle - overview The Control Unit orchestrates the complete execution of each instruction: – At its heart is a Finite State Machine that sets up the state of the logic circuits according to each instruction. – This process is governed by the system clock - the FSM goes through one transition (“machine cycle”) for each tick of the clock. Six phases of the complete Instruction Cycle (and repeat…) – Fetch: load IR with instruction from memory – Decode: determine action to take (set up inputs for ALU, RAM, etc.) – Evaluate address: compute memory address of operands, if any – Fetch operands: read operands from memory or registers – Execute: carry out instruction – Store results: write result to destination (register or memory) CEG/EE 260 - 91 Instruction Cycle - steps 1 & 2 Fetch – The first step is to read an instruction from memory. – This actually takes several smaller steps, or “micro-instructions”: MAR ← (PC) ; use the value in PC to access memory PC ← (PC) + 1 ; increment the value of PC MDR ← Mem[MAR] ; read memory location to MDR IR ← (MDR) ; copy (MDR) to IRDecode – Steps 1, 2 & 4 take a single machine cycle each, but step 3 (memory access) can take many machine cycles. Decode – The opcode is input to a decoder, which sets up the ensuing sequence of events according the instruction. CEG/EE 260 - 92 Instruction Cycle - steps 3 & 4 Evaluate Address – Computes the address of the operand (if any), or of the memory location to be accessed: e.g. the location from which to obtain a value in a LOAD instruction. This is known as the Effective Address (EA). Register to Register instructions don’t have an evaluate address phase. Fetch Operands – Obtains the source operand(s), if required for execution. – Operands can come from Registers or RAM, or be embedded in the instruction itself. The Effective Address (EA) determined in the previous step may be used to obtain an operand from memory. CEG/EE 260 - 93 Instruction Cycle - steps 5 & 6 Execute – Now that everything is in place, the instruction is executed. e.g. if the opcode was ADD, the two source operands are added by the ALU. If the opcode was a control instruction, a value is written to the PC Data Movement instructions don’t have an execute phase Store Result – If there is a result from the operation it is written to memory (using the EA), or to a register. Then REPEAT – The control unit just keeps repeating this whole process: Recall that the PC was incremented in the first step (FETCH), so the instruction retrieved will be the next in the program as stored in memory - unless the instruction just executed changed the contents of the PC. CEG/EE 260 - 94 Types of Instruction Operate Instructions – process data (addition, logical operations, etc.) Data Movement Instructions … – move data between memory locations and registers. Control Instructions … – change the sequence of execution of instructions in the stored program. The default is sequential execution: the PC is incremented by 1 at the start of every Fetch, in preparation for the next one. Control instructions set the PC to a new value during the Execute phase, so the next instruction comes from a different place in the program. This allows us to build control structures such as loops and branches. CEG/EE 260 - 95 Stopping the computer – “User” programs terminate simply by handing control back to the Operating System (OS): The OS then enters a “waiting” loop until a new program is run. The Control Unit is still actively stepping through the instruction cycle. – Left to itself, the control unit would just keep fetching instructions from memory … until we pull the plug! We can cease processing completely by stopping the machine cycle - i.e. by stopping the clock.