Download Common Parameters - Microelectronic Devices and Circuits - Exam and more Exams Microeconomics in PDF only on Docsity! University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EE 105 Midterm I Spring 2007 Prof. Ming C. Wu Feb. 22, 2007 Guidelines • Open book and notes. • The values of common parameters are listed at the beginning of next page. 1 Please use the following parameters for all problems unless specified otherwise: φn+ = 550 mV, φp+ = -550 mV, Vth = 26 mV εSi = 11.7, εSiO2 = 3.9, ε0 = 8.854×10-14 F/cm, q = 1.6x10-19 C, ni = 1010 cm-3. (1) The figure below shows the schematic cross section of a CMOS device. a) [5 pt] Please circle all the PN junctions in this CMOS device directly on the cross- sectional diagram in your answer sheets. How many PN junctions are there? b) [5 pt] If the power supply voltages available for this CMOS are +2V and -2V, what voltage should be applied to VA and VE? Why? P-type Substrate (P= 1016 cm-3) N-type Well (N=1017 cm-3) P+ P+ N+N+N+P+ P+ PolyN+ Poly VA VB VD VEVC VD (2) Consider a PN junction with both N and P doping concentration of 1016 cm-3. a) [5 pt] Find the built-in potential. b) [5 pt] What is the depletion width at zero bias? c) [5 pt] What is the maximum electric field at zero bias? d) [5 pt] The PN junction is used as a varactor. If the bias voltage is varied from zero to 10V reverse bias, what is the capacitance tuning ratio (i.e., the ratio of maximum and minimum capacitance) (3) Consider a PMOS capacitor with a p+ poly gate and a 1-nm-thick high-k gate dielectric whose relative dielectric constant is 20. The substrate doping is 1016 cm-3. a) [5 pt] Find the flat-band voltage. b) [5 pt] Find the threshold voltage. c) [10 pt] Find the charge distribution of the MOS capacitor (i.e., ( )xρ vs x ) when the gate is biased at 0V. Please be quantitative. d) [5 pt] What is the total gate charge per unit area at the gate, channel, and body, respectively, when the gate is biased at 0V. e) [5 pt] What is the total capacitance per unit area when the gate is biased at 0V? (4) For the circuit shown below, W/L = 10 for both M1 and M2, n oxCμ = 100 μA/V 2, p oxCμ = 50 μA/V 2, λ = 0.05 V-1 for NMOS and 0.01 V-1 for PMOS, VTH = 1V for NMOS and -1V for PMOS, VDD = 5V. 2
