Comparators - Principles of Computer Architecture - Lecture Slides, Slides of Advanced Computer Architecture

Download Comparators - Principles of Computer Architecture - Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! Comparators – A comparator compares two input words. – The following slide shows a simple comparator which takes two inputs, A, and B, each of length 4 bits, and produces 1 if they are equal and a 0 if they are not equal. • The circuit is based on the XOR gate (EXCLUSIVE OR) gate, which puts out a 0 if its inputs are equal and a 1 if they are unequal. • If the two words are equal, all four of the XOR gates must output 0. The results are then combined with a NOR gate. Docsity.com Comparators Bs EXCLUSIVE OR gate yuo Y Figure 3-14. A simple 4-bit comparator. Docsity.com Programmable Logic Arrays • The output consists of six OR gates, each of which has up to 50 inputs, corresponding to the 50 outputs of the AND gates. Once again a user supplied (50 x 6) matrix determines which connections actually exist. • A PLA can be used to compute the majority function described previously. Examine the diagram for the circuit. By using just 3 of the 12 PLA inputs, four of its 50 AND gates, and one of its six OR gates, we can implement the circuit. Actually, we could wire the PLA to compute simultaneously a total of four functions of similar complexity. Docsity.com Programmable Logic Arrays – Field-programmable PLAs (shipped from the factories with all fuses intact and then programmed by the user) are still in use, but for many applications custom-made PLAs are preferable. • These are designed by the (large-volume) customer and fabricated by the manufacturer to the customer’s specifications. Such PLAs are cheaper than field- programmable ones. – We have seen three ways to compute the majority function. Docsity.com Arithmetic Circuits • We now move from general-purpose MSI circuits to MSI combinatorial circuits used for doing arithmetic. – The first arithmetic MSI circuit we will examine is an eight-input, eight-output shifter. – Eight bits of input are presented on lines D0, … , D7. The output, which is just the input shifted 1 bit is available on lines S0, … , S7. The control line, C, determines the direction of the shift, 0 for left and 1 for right. Docsity.com Adders ps - GSview File Edt Options View Orientation Media Help File: figs-3 pe 434, 460pt_ Page: "18" 18 of 58 Exclusive OR gate B | Sum |Carry| oe Qo a [@ESLOL@] andi) + |e} | = |e] ee a Carry Figure 3-17. (a) Truth table for 1-bit addition. (b) A circuit for a half adder. [x nie Docsity.com Adders – A half adder is adequate for summing the low- order bits of two multiple input words, it will not do for a bit position in the middle of the word because it does not handle the carry into the position from the right. – For this, we need the full adder. A full adder is built up from two half adders. – Together the two half adders generate both the sum and the carry bits. Docsity.com Adders Carry in Carry| Carry A B In | 24) out A Ty ms Sum ofofofolo B } , 0 Qo 1 1 a 0 1 o 1 a 0 1 1 0 1 1 Qo Q 1 a 1 Qo 1 0 1 1 1 0 0 1 1 1 1 1 1 Carry out (a) () Figure 3-13. (a) Truth table for full adder. (b) Circuit for a full addet. Docsity.com Arithmetic Logic Units – Most computers contain a single circuit for performing the AND, OR, and sum of two machine words. Typically, such a circuit for n-bit words is built up of n identical circuits for the individual bit positions and is called an Arithmetic Logic Unit or ALU. – An ALU capable of computing A AND B, A OR B, B’, or A + B, depending on the function select lines F0 and F1 is shown on the following slide. Docsity.com Arithmetic Logic Units 2 ps - GSview File Edit Options View Orientation Media Help Fle: figs 3p Sal, 27Gpt_ Page: "20" 20 of 68 Logical unit carry in 4] 2 Ea AB 2? | INVA ge A Output + ENA. ye B _ ENB +5) = ee] | Enable, Fo A Decoder Cary out Figure 3-19. A 1-bit ALU. Docsity.com Arithmetic Logic Units – The lower left-hand corner of the ALU contains a 2-bit decoder to generate enable signals for the four operations, based on the control signals F0 and F1. Exactly one of the four enable lines is selected. – A or B can be forced to 0 by negating ENA or ENB, respectively. It is also possible to get A’, by setting INVA. Under normal conditions, ENA and ENB are both 1 to enable both inputs and INVA is 0. We will later see uses for INVA, ENA, and ENB. Docsity.com Clocks – In many digital circuits the order in which events happen is critical. – To allow designers to achieve the required timing relations, many digital circuits use clocks to provide synchronization. – A clock is a circuit that emits a series of pulses with a precise pulse width and precise interval between consecutive pulses. • The time interval between the corresponding edges of two consecutive pulses is known as the clock cycle time. Docsity.com Clocks – Pulse frequencies are commonly between 100 MHz and 4 GHz, corresponding to clock cycles of 10 nsec to 250 psec. • To achieve high accuracy, the clock frequency is usually controlled by a crystal oscillator. – In a computer, many events may occur during a single clock cycle. If these events must occur in a certain order, the clock cycle must be divided into subcycles. A secondary clock signal phase-shifted from the primary may be generated with a delay circuit. Docsity.com Clocks £ 4 - A — j--4---- oO oO a _ 7 — ef o a fe _ B sy —---4---- ro qm o o (c) Figure 3-21. (a) A clock. (b} The timing diagram for the clock. (c} Generation of an asymmetric clock. Docsity.com Latches – The circuit on the next slide is called an SR latch. • It has two inputs, S, for Setting the latch and R, for Resetting it. • It also has two outputs, Q and Q’, which are complementary. • Unlike a combinatorial circuit, the outputs of the latch are not uniquely determined by the current inputs. • Assume that both S and R are 0. Assume that Q = 0. Because Q is fed back into the upper NOR gate, both of its inputs are 0, so its output is 1. Docsity.com Latches el (al (b) (ce) Figure 3-22. (a) NOR latch in state 0. (b} NOR latch in state 1. tc) Truth table for NOR. Docsity.com Latches • Now imagine that Q is not 0 but 1, with R and S still 0. The upper gate has inputs of 0 and 1, and an output of 0, which is fed back to the lower gate. • A state with both outputs equal to 0 is inconsistent, because it forces both gates to have two 0s as input, which, if true, would produce 1, not 0, as output. • Similarly, it is impossible to have both outputs equal to 1. • The conclusion: for R = S = 0, the latch has two stable states, which we will refer to as 0 and 1, depending on Q. Docsity.com Latches 8 Q Clock JL —+ Q R Figure 3-23. A clocked SR latch Docsity.com Latches – When both S and R are 1, the circuit becomes nondeterministic. – A variant, the clocked D latch prevents the situation from occurring Docsity.com Latches Figure 3-24. A clocked D latch Docsity.com