Managing Complexity in Designing Digital Systems: Datapath, Control Unit, and Implementati, Study notes of Digital Systems Design

Download Managing Complexity in Designing Digital Systems: Datapath, Control Unit, and Implementati and more Study notes Digital Systems Design in PDF only on Docsity! CEG 360/560; EE 451/651 Digital System Design Dr. Travis Doom, Associate Professor Department of Computer Science and Engineering Wright State University Section III: Complex system design CEG 360/560 - EE 451/651 Section III - 2 Outline Dealing with Complexity Data unit (Datapath) design – Registers – RTL language – Datapath Construction Control unit (Controller) design – ASM Charts Implementation issues – PLDs – ROM – VLSI Design CEG 360/560 - EE 451/651 Section III - 3 Dealing with Complexity Practical synchronous sequential circuits are too complex to design at the flip-flop level. – A simple 8-bit CPU capable of storing only four values (in four GPRs) has at least 4 x 8 = 32 1-bit state devices! – If the CPU had only 8 inputs it would still require a 232 by 28 truth table to represent the device. Each of these billion or so entries would have to contain a 32-bit next state. Storing 240 32-bit entries would require 4 TB! K (kilo) 210 1024 M (mega) 220 1048576 G (giga) 230 1.07 x 109 T (tera) 240 1.10 x 1012 – Simplification would require a 40-variable K-map! How do we manage complex design? CEG 360/560 - EE 451/651 Section III - 4 Complex System Design Practical sequential designs, like combinational designs, require a hierarchical approach – Use well defined building blocks Complex blocks made of simpler blocks (hierarchy) Examples: Registers, counters Associate a high-level of behavior with those blocks (abstraction) – Design methodologies based on abstractions can more easily encompass complexity – Common function blocks: registers and counters ORDER a sequence of high-level behaviors that (when executed in the proper order) solves the overall problem – Like computer programming! CEG 360/560 - EE 451/651 Section III - 5 Decomposing a Design: Control and Data Complex designs are generally broken down into to high-level abstractions. – The datapath is home to one or more datapath components that provide higher-level functionality (viewable at the register transfer level) – The control unit controls the sequence in which the datapath functions are performed in order to perform the system task Control Unit Datapath Control Signals Status Signals Control Outputs Data Inputs Control Inputs Data Outputs CEG 360/560 - EE 451/651 Section III - 6 Outline Dealing with Complexity Data unit (Datapath) design – Registers – RTL language – Datapath Construction Control unit (Controller) design – ASM Charts Implementation issues – PLDs – ROM – VLSI Design CEG 360/560 - EE 451/651 Section III - 13 Octal Tri-state Register/Latch CLK OE 74LS374 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C OE 74LS373 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1Q 2Q 8Q D Q D Q D Q 1D 2D 8D /OE CLK 74LS374 CEG 360/560 - EE 451/651 Section III - 14 Shift Register Applications State Registers – Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position – Very effective for finite memory machines Serial Interconnection of Systems – keep interconnection cost low with serial interconnect Bit Serial Operations – Bit serial operations can be performed quickly through device iteration – Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). – A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation CEG 360/560 - EE 451/651 Section III - 15 Shift Register Applications SDATA Parallel- to-serial converter Parallel Data from A-to-D converter Serial-to- parallel converter Parallel Data to D-to-A converter Control Circuits CLOCK /SYNC Transmitter Control Circuits Receiver CLOCK - 1 bit per clock tick = 2.048 MHz /SYNC - synchronization of start of “frame” SDATA - serial data stream DIGITAL TELEPHONY CEG 360/560 - EE 451/651 Section III - 16 Shift Register Applications ...7 6 5 0 > x7 x6 x5 x0 ...7 6 5 0 > y7 y6 y5 y0 ...7 6 5 0 > FA Cout S Cin A BD Q CLK CLR CLK CLEAR_C z7 z6 z5 z0... CTL Sequential Implementation of: Z[7..0] = X[7..0] + Y[7..0] V CEG 360/560 - EE 451/651 Section III - 17 Counters Counters are registers with extra functions Clocked sequential circuit with single-cycle state diagram – Modulo-m counter = divide-by-m counter Most Common: n-bit binary counter, where m = 2n n flip-flops, counts 0 … 2n-1 S3 S2 S1 Sm 111 110 101 100 011 010 001 000 CEG 360/560 - EE 451/651 Section III - 18 Counting Common output codes for mod-8 and decimal counters State Binary BCD Gray Excess-3 Ring Twisted-tail 0 000 0000 000 0011 00000001 0000 1 001 0001 001 0100 00000010 0001 2 010 0010 011 0101 00000100 0011 3 011 0011 010 0110 00001000 0111 4 100 0100 110 0111 00010000 1111 5 101 0101 111 1000 00100000 1110 6 110 0110 101 1001 01000000 1100 7 111 0111 100 1010 10000000 1000 8 1000 1011 9 1001 1100 CEG 360/560 - EE 451/651 Section III - 19 Asynchronous/Ripple Counter Q Q T Q Q T Q Q T Q Q T CLK Q0 Q1 Q2 Q3 1 bit divide-by-2 2 bit divide-by-4 3 bit divide-by-8 4 bit divide-by-16 Uses Minimal Logic! Tpd = n x Tpd,tff Setup = Tsetup,tff CEG 360/560 - EE 451/651 Section III - 20 Synchronous Counters All clock inputs connected to common CLK signal – So all flip-flop outputs change simultaneously tCQ after CLK Synchronous Counters are/have – Faster – More Complex Logic (more “expensive”) – Most Frequently Used Type of Counter Two types of synchronous counters – Serial – Parallel Easy to combine iteratively to build bigger counters – Combined counters have serial aspects. If the devices are parallel, then the overall device is “mixed mode”. CEG 360/560 - EE 451/651 Section III - 21 Synchronous Serial Counter Flip-flops enabled when all lower flip- flops = 1. Enable propagates serially — limits speed Requires (n-1) Δ t < TCLK All outputs change simultaneously tCQ after CLK >T QEN CLK CNTEN Q0 Q1 Q2 Q3 QEN >T QEN >T QEN >TEquation? Delay? Δ t Δ t Δ t Tpd = Tpd,tff Tsetup = (n-1)Δt + Tsetup,tff CEG 360/560 - EE 451/651 Section III - 28 Modulo-11 Counter [0,1,2, …, 10, 0, 1, ...] >CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 74X163 CLOCK +5 V Q0 Q1 Q2 Q3 When Count=10 Clear Decode Count 1x1x (10…15) Q3 • Q1 CEG 360/560 - EE 451/651 Section III - 29 Cascaded 74163s for 8-bit Counter Up to Modulo-256 >CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 74X163 >CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 74X163 CLOCK /RESET /LOAD CNTEN D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RCO8 CEG 360/560 - EE 451/651 Section III - 30 4-bit, 8-state Johnson Counter Also known as – twisted-ring counter – Moebius counter 2n states with n flip-flops – NOT self-correcting RIN A B C D LIN S0 S1 CLR CLK +5 V R 74X194 CLOCK QA QB QC QD Wired as a shift-left shift register Q0 Q1 Q2 Q3 /RESET 74X04 CEG 360/560 - EE 451/651 Section III - 31 Design Decomposition A digital system is a sequential circuit with specified behavior. – A microprocessor is a digital system. Specifying large digital systems with state tables may be exceptionally difficult, due to the number of states involved. – As in computer programming, most digital systems are designed using a modular, hierarchical approach. – The system is partitioned into modular subsystems. Each subsystem performs a well defined function with specified interface. – Interconnection the various subsystems though data and control signals results in a digital system. CEG 360/560 - EE 451/651 Section III - 32 Design Decomposition Most digital systems are partitioned into two top-level modules: – Data Unit (or Datapath): performs data-processing operations. – Control Unit: determines the sequence of these operations. Datapaths are sequential systems. – the system state is defined by the contents of the registers. – the functionality is the set of defined operations that can be performed on the contents of the registers. – Elementary operations are usually, but not always, performed in parallel on a string of bits in one clock tick. A microoperation is an elementary operation performed on data stored in the datapath. They fall into four general categories: – Transfer microoperations: transfer binary data from one register (or data input/memory) to another. – Arithmetic microoperations: perform arithmetic on data in registers. – Logic microoperations: perform bit manipulations on data in registers. – Shift microoperations: shift data in registers. CEG 360/560 - EE 451/651 Section III - 33 Register-Transfer Level Design An approach to specify, analyze, and design systems too complex to use the state-table based approaches commonly utilized in “simple” designs. The Register-Transfer Level (RTL) approach is characterized by: – A digital system is viewed as divided into a data subsystem and a control subsystem. – The state of the data subsystem consists of the contents of the registers. – The function of the system is performed as a sequence of register transfers. – A register transfer is a transformation performed on the datum while the datum is transferred from one register to another. – The sequence of register transfers is controlled by the control subsystem. The operation of the device can be designed as a sequence of register transfers can be designed using state diagrams, ASM charts, etc. – Each transfer must correspond to a sequence of microoperations. – The control unit implements the RTL design through microoperations. CEG 360/560 - EE 451/651 Section III - 34 RTL Languages (1) The notation for register transfers are sufficiently complete to describe any digital system at the register-transfer level. – known as register-transfer languages. Registers are denoted by uppercase letters (sometimes followed by numbers) that indicate the function of the register – e.g. R0, R1, AR, PC, MAR, et al. – The individual bits can be denoted using parenthesis and bit numbers or labels e.g. R0(0), R0(7:0), PC(L), PC(H) Data transfer is denoted in symbolic form by the means of the replacement operator ←. – e.g. R2 ← R1 CEG 360/560 - EE 451/651 Section III - 35 RTL Languages (2) Normally we want a given transfer to occur not for every clock pulse, but only for specific values of the control signals. – RTL conditional statements: e.g. If (K1 = 1) Then (R2 ← R1) – Control function notation (Colon, :) e.g. K1: R2 ← R1 All RTL statements occur in response to a clock tick. A comma is used to separate two or more register transfers that are executed at the same time. A semi-colon is used for an instruction with different control – e.g. Brake: R2 ← R1, R4 ← R3; not(Brake): R1 ← R2 CEG 360/560 - EE 451/651 Section III - 36 RTL Languages (3) Register to Memory Transfers are denoted using square brackets surrounding the memory address. – e.g. DR ← M[AR] (Read operation) – e.g. M[AR] ← SR (Write operation) CEG 360/560 - EE 451/651 Section III - 43 Outline Dealing with Complexity Data unit (Datapath) design – Registers – RTL language – Datapath Construction Control unit (Controller) design – ASM Charts Implementation issues – PLDs – ROM – VLSI Design CEG 360/560 - EE 451/651 Section III - 44 Interaction between Data and Control Units Control Signals - signals that activate data-processing functions. – To activate a sequence of such operations, the control unit sends the proper sequence of control signals to the datapath. Status Signals - signals that describe aspects of the state of the datapath. – The control unit uses these signals in determining the specific sequence of operations to be performed. Other Signals - allow the control unit and datapath to interact with other parts of the system, such as memory and input-output logic. Control Unit Datapath Control Signals Status Signals Control Outputs Data Inputs Control Inputs Data Outputs CEG 360/560 - EE 451/651 Section III - 45 The Control Unit The control unit generates the signals for sequencing the operations in the datapath – A sequential circuit with states that dictate the control signals for the system – Using status conditions and control inputs, the sequential control unit determines the next state in which additional microoperations are activated. Hardwired Control – The control unit is implemented to provide a particular digital function Microprogrammed Control – LATER! CEG 360/560 - EE 451/651 Section III - 46 Control Unit Design Control unit Next State StartOverflow = PS 00 01 10 11 RTL IDLE IDLE IDLE S1 S1 S1 S2 S2 S2 S2 Rx ← max (A, B) S2 S3 S3 S3 S3 Ry ← min (A, B) S3 S4 S4 S4 S4 Ry ← Ry >> 1 S4 S5 S5 S5 S5 Rt ← Rx >> 3 S5 S6 S6 S6 S6 Rt ← Rx – Rt S6 S7 ERR S7 ERR Rt ← Ry + Rt S7 S8 S8 S8 s8 Rc ← max (Rx, Rt) S8 IDLE IDLE IDLE IDLE C ← Rc; Done ← 1 ERR IDLE IDLE IDLE IDLE ERR ← 1Start Overflow Done LDx … CEG 360/560 - EE 451/651 Section III - 47 ASM for Control Control unit … Rx ← max (A, B) Ry ← min (A, B) Ry ← Ry >> 1 Rt ← Rx >> 3 Rt ← Rx – Rt Rt ← Ry + Rt Rc ← max (Rx, Rt) C ← Rc; DONE ← 1 … Rx ← max (A,B) Ry ← max (A,B) Ry ← Ry >> 1 Rt ← Rx >> 3 . . . LDRx, MXC1=0, MC2=0, MXF=1 LDRy, MXC1=0 MC2=0, MXF=0 LDRy, MXS=0, SR1,3 = 0 LDRt, MXS=1, SR1,3 = 1 . . . CEG 360/560 - EE 451/651 Section III - 48 Algorithmic State Machines Algorithmic State Machine (ASM) Chart – Special flowchart used to define digital hardware algorithms – Describes a sequence of events – Determines the actions which occur in the states in response to the clock pulse in response to changes in the inputs ASM Charts contain three basic elements: – State boxes Rectangles, labeled with the state name and assignment, containing a register operation and/or the names of Moore outputs asserted in that state. – Decision boxes Diamonds containing a conditional input expression and exits 1 and 0. – Conditional output boxes Ovals containing Mealy outputs asserted for the conditions leading to the box. CEG 360/560 - EE 451/651 Section III - 49 ASM elements Moore output list state name state code state entry path state exit path State box condition condition Decision box 0 1 0 1 OR condition false exit path condition true exit path conditional output list from decision-box exit path exit path Conditional (Mealy) output box CEG 360/560 - EE 451/651 Section III - 50 ASM Timing Each state box has a corresponding “ASM Block” that includes all decision and conditional output boxes reached from that state – Each ASM Block has exactly one state box, all paths leaving the ASM Block lead directly to a different state box. The current state box represents the current state. The current inputs decide a path through the decision boxes. – Unlike state diagrams, ambiguity is easily avoided in ASM charts. – Conditional outputs along the path occur immediately in response to changes in the inputs values. The next state box is not entered until a clock tick occurs. – The Moore outputs in the state box and any conditional (Mealy) outputs in the new ASM Block are asserted immediately. ASM boxes may also include Register Transfer directives! – Any changes (conditional or otherwise) to a sequential device wait until the next positive clock edge. CEG 360/560 - EE 451/651 Section III - 51 ASM Example: 4-bit binary counter Z1,Z0 STATE = Q1 Q0 00 01 10 11 A B C D Z0 Z1 Z=3 STATE = Q1 Q0 00 01 10 11 A B C D Z=1 Z=2 -or- Z=0 CEG 360/560 - EE 451/651 Section III - 58 Example: 1’s Counter Q1Q0 INPUT Q1*Q0* 00 (XY) 10 00 (XY)’(X+Y) 01 00 (XY)’(X+Y)’ 00 01 (XY) 11 01 (XY)’(X+Y) 10 01 (XY)’(X+Y)’ 01 10 (XY) 00 10 (XY)’(X+Y) 11 10 (XY)’(X+Y)’ 10 11 (XY) 01 11 (XY)’(X+Y) 00 11 (XY)’(X+Y)’ 11 Q1* = Q1’Q0’(XY) + Q1’Q0(XY) + Q1’Q0(XY)’(X+Y) + Q1Q0’(XY)’(X+Y) + Q1Q0’(XY)’(X+Y)’ + Q1Q0(XY)’(X+Y)’ Q2* = Q1’Q0’(XY)’(X+Y) + Q1’Q0(XY) + Q1’Q0(XY)’(X+Y)’ + Q1Q0’(XY)’(X+Y) + Q1Q0(XY) + Q1Q0(XY)’(X+Y)’ + CEG 360/560 - EE 451/651 Section III - 59 Outline Dealing with Complexity Data unit (Datapath) design – Registers – RTL language – Datapath Construction Control unit (Controller) design – ASM Charts Implementation issues – PLDs – ROM – VLSI Design CEG 360/560 - EE 451/651 Section III - 60 Programmable Logic Definitions Digital integrated circuit (MSI, LSI, VLSI) – manufactured as a standard off-the-shelf component – containing “regular” array of logic gates and flip-flops – whose logic functions are determined by the application design engineer and implemented locally Many types of programmable logic – sometimes generically called PLDs (Programmable Logic Devices) – PAL or PLD – PROM – FPGA output input Combinational PLD CEG 360/560 - EE 451/651 Section III - 61 Programmable Logic Definitions PLA – Programmable Logic Array – first PLDs – simple programmable AND/OR array – programmed by “blowing fuses” by hand or by mask CEG 360/560 - EE 451/651 Section III - 62 PAL – Programmable Array Logic – similar to a PLA, but the OR- array is fixed – most commonly used PLD – may include input/output flip- flops GAL – Generic Array Logic – can be configured to emulate the AND/OR, flip-flop, and output structure of a variety of combinational and sequential PAL devices Programmable Logic CEG 360/560 - EE 451/651 Section III - 63 Read-Only Memory (ROM) A combinational circuit with n inputs and b outputs: 2n x b ROM Address inputs A(n-1, ... , 0) n b Data outputs D(b-1, ... , 0) Programmable ⎯ values determined by user Nonvolatile ⎯ contents retained without power Uniform (Random) Access ⎯ delay is uniform for all addresses CEG 360/560 - EE 451/651 Section III - 64 Read-Only Memory (ROM) Two views: – ROM stores 2n words of b bits each, or – ROM stores an n-input, b-output truth table Example: A1 A0 D3 D2 D1 D0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Stores 4 4-bit words, or stores 4 functions of 2 input variables b = 4n = 2 CEG 360/560 - EE 451/651 Section III - 65 Using ROMs for Combinational Logic A 3-input, 4-output combinational logic function: Function: 2-to-4 Decoder with Polarity Control A2 = Polarity (0 = active Low, 1= active High) A1, A0 = I1, I0 (2-bit input ) D3...D0 = Y3...Y0 (4-bit decoded output) Inputs Outputs A2 A1 A0 D3 D2 D1 D0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 8 × 4 ROM A0 D0 A1 D1 A2 D2 D3 Y0 I1 POL Y1 Y2 Y3 I0 CEG 360/560 - EE 451/651 Section III - 66 Internal Structure of 4×4 Diode ROM D0 D1 D2 D3 2 to 4 Decoder A1 A0 Bit Lines /w0 /w1 /w2 /w3 Diode 1 No Diode 0 0101 0001 1000 1111 1 of n Word Lines R0R1R2R3 +5 V Why use diodes? Why not replace them with wires? CEG 360/560 - EE 451/651 Section III - 73 Consider a 64 x 1 ROM Very tall, narrow chip (BAD) Even worse for larger chips! How can we make it more square? This Decoder needs 64 6-input gates! +5 V 6-to-64 Decoder /w0 /w1 /w63 A5 A0 •• • 64 x 1 Diode Array D0 CEG 360/560 - EE 451/651 Section III - 74 64 x 1 ROM with 2-Dimensional Decoding Almost square chip! 3 to 8 Decoder /w0 /w1 /w7 +5 V 0 7 8 to 1 mux A5 A3 A2 A0 D0 • • • • • • Decoder and mux = 8 3-input gates + 8 4-input gates 8 x 8 Diode Array CEG 360/560 - EE 451/651 Section III - 75 64K x 8 ROM with 2-D Decoding 9 to 512 Decoder A A 9 7 512 512 × 128 128 to 1 Mux • •• • • • D0 D1 D7 512 × 128 512 × 128 512 × 1024 Array 128 to 1 Mux 128 to 1 Mux 128 128 128 Is this a square chip? 2-D Decoding / Coincident selection 64k x 8 = 216 * 23 = 219 square root (219) ~= 29 CEG 360/560 - EE 451/651 Section III - 76 Internal 2n x b ROM Control Structure Row decoder Power on Storage array Column multiplexer A0 A1 Am-1 Am Am+1 An-1 /CS /OE Db-1 Db-2 D0 Power on Power on CEG 360/560 - EE 451/651 Section III - 77 Programmable Logic Advantages – Design flexibility – Better design automation – Higher density, fewer packages (compared to SSI-MSI) – Less expensive – Lower power – Higher performance Programming Technologies – Interconnections usually made by pass transistors controlled by memory bits of some type: – Antifuse - permanent connections made electrically – EPROM - charged floating gate, UV erasable – EEPROM - charged floating gate, electrically erasable – Flash Memory - charged floating gate, electrically erasable – Programmed using CAD - Hardware Description Languages CEG 360/560 - EE 451/651 Section III - 78 Modern (VLSI) Design The VLSI chips that are used in most modern designs come in three varieties: – Custom Approach: VLSI chips, or some of their parts, are designed by hand. Full Custom Vs. Standard Cell - Using standard cell designs (same height, variable width) and routing channels simplifies the design process Highest Density, Highest Manufacturing Cost – Semicustom Approach: The VLSI chips employ gate arrays and technology mapping. Gate array: a partially prefabricated IC that incorporates a large number of identical gates (usually 3-input NAND or NOR gates) that are laid out in a regular two-dimensional array. Technology mapping: The process of designing a logic function as a network of available devices. Lower Density (10-25% more gates than an equivalent custom design). Inexpensive: Requires only metal deposition (define interconnections), economy of scale. CEG 360/560 - EE 451/651 Section III - 79 Modern (VLSI) Design The VLSI chips that are used in most modern designs come in three varieties: – VLSI PLDs Field Programmable Gate Arrays (FPGAs) A VLSI modules that can be programmed to implement a digital system consisting of tens of thousands of gates. LSI PLDs implement two-level combinational and sequential networks, FPGAs allow the realization of multilevel networks and complex systems on a single chip! Highly reprogrammable! Low cost May produce slower network May require a larger silicon area