Computer Architecture & Design Homework Solutions for ELEC 5200-001/6200-001, Spring '07 -, Assignments of Computer Architecture and Organization

Download Computer Architecture & Design Homework Solutions for ELEC 5200-001/6200-001, Spring '07 - and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2007 Homework 10 Solutions Assigned 4/24/07, due 4/30/07 Problem 1: (a) Consider a processor connected directly to the main memory. Each memory access (read or write) requires 50 cycles. Besides the instruction fetch, needed for every instruction, 25% instructions require an additional memory data access. Neglecting structural hazards, what is the average number of cycles an instruction uses for memory accesses? (b) To reduce structural hazards, we use separate one-level caches for instruction and data, with access times of 1 cycle each. The cache sizes and organizations are such that the hit rates for both instruction and data caches are 0.95. The miss penalty (time to refresh and access the cache) is 100 cycles for each cache. What is the average number of memory access cycles per instruction now? (c) If we were to reduce the miss penalty of just one of the caches, which one should it be – the instruction cache or the data cache? Why? Answer: (a) Average memory access cycles per instruction = 50 + 0.25×50 = 62.5 (b) Average memory access cycles per instruction = 0.95×1 + 0.05×100 + 0.25(0.95×1 + 0.05×100) = 7.4375 (c) We should improve the instruction cache because every instruction is fetched, while the data access is required only by 25% of instructions. Problem 2: (a) Consider a two-level cache system in which the L1 cache has a hit rate h. The hit rate for L2 cache is 0.9h. The access time from the L1 cache is one clock cycle. The access time from L2 cache (i.e., bringing data from L2 to L1 and then reading from L1) is ten times that for the L1 cache. The access time from the main memory (i.e., transferring data from memory to L2, L2 to L1, and then to processor) is ten times that for the L2 cache. Show that the average time for a memory operation is 100 – 180h + 81h2.