Computer Architecture and Design: Homework 8 Solutions - Spring 2009 - Prof. Vishwani Agra, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design: Homework 8 Solutions - Spring 2009 - Prof. Vishwani Agra and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2009 Homework 8 Solution Assigned 4/17/09, due 4/24/09 Problem 1: A processor chip is used for applications in which 30%of execution time is spent on floating point additions, 25% on floating point multiplications, and 10% on floating point division. For the new model of the processor, the design team has come up with three possible enhancements, each costing about the same in design effort and manufacturing. Which enhancement should be chosen? a. Redesign the floating point adder to make it twice as fast. b. Redesign the floating point multiplier to make it three times as fast. c. Redesign the floating point divider to make it ten times as fast. Solution: We can apply Amdahl’s law Speedup = 1/[(1 – f) + f/n] to three options, using f = 0.3, 0.25 and 0.1, respectively, for the speeded up fraction in the three cases. a. Speedup for adder redesign = 1/[0.7 + 0.3/2] = 1.18 b. Speedup for multiplier redesign = 1/[0.75 + 0.25/3] = 1.20 c. Speedup for divider redesign = 1/[0.9 + 0.1/10] = 1.10 The floating point multiplier gives the most performance advantage and should be chosen. Problem 2: Run times of three programs are recorded for two processors: Run time Performance Program Processor X Processor Y X over Y Y over X A 20 200 10.0 0.1 B 1000 100 0.1 10.0 C 1500 150 0.1 10.0 Calculate composite performance ratios for X/Y and Y/X and determine which processor has a higher performance? Solution: Using the geometric mean formula: Performance X/Y = (10.0 × 0.1 × 0.1)1/3 = 0.46 Performance Y/X = (0.1 × 10.0 × 10.0) = 2.15 Y has higher performance. Problem 3: Consider n processor cores in a distributed memory system. The compiler distributes instructions of a program to processors such that independent executions are possible. However, after the execution the individual processor register files may contain inconsistent data. Inter-processor communication copies any changes before the execution of the next instruction. For n processors, because each processor communicates with n – 1 other processors, a time overhead β(n – 1) should be added to the instruction execution time, where has some small positive value. Show that such parallel processing corresponds to Amdahl’s law in which the fraction that cannot be speeded up is βn. Further show that for very small values of the inter-processor communication factor β, the maximum speedup ≈ n/2. What are the maximum speedups and the corresponding values of n for β = 0.1, 0.01, 0.001, etc.? Solution: We assume that K instructions are equally distributed to n processors. Then, K 1 Speedup =  =  (1) (K/n) + Kβ(n – 1) (1/n) + β(n – 1) Comparing this with Amdahl’s original formula: 1 Speedup = —————— (2) 1 – fenh + fenh/n we equate the denominators and find fenh = 1 – βn. Therefore, the unparallelizable fraction of computing task that cannot be speeded up is 1 – fenh = βn. Next, to find n for maximum speedup, we differentiate the denominator of (1) with respect to n and set it to 0. Thus, – (1/n2) + β = 0, or n = √ (1/β) This minimizes the denominator in (1) because the second derivative 2/n3 is positive. Substituting the optimizing number of processors in (1), we get for small β 1 1 Maximum speedup =  ≈  = n/2, where n = √ (1/β) √β + √β – β 2√β For β = 0.1, optimum n is 3, and maximum speedup is 1.875. For β = 0.01, optimum n is 10, and maximum speedup is 5.26. For β = 0.001, optimum n is 32, and maximum speedup is 16.06 ≈ n/2.