Computer Architecture and Design Homework 4 Solutions for ELEC 5200-001/6200-001 - Prof. V, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design Homework 4 Solutions for ELEC 5200-001/6200-001 - Prof. V and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2008 Homework 4 Solution Assigned 2/20/08, due 2/27/08 Problem 1: A single-cycle MIPS datapath is designed to execute the simple unconditional jump (j) instruction. What extra hardware, if any, will you add for the execution of the jump and link (jal) instruction? Give a schematic in which you may include only those units that participate in the execution of the jal instruction Answer: The MIPS jal instruction (opcode = 000011) does two things: 1. Writes PC+4 in the return address register ra (#31 in register file). 2. Multiply the 26-bit argument by 4 (i.e., shift left 2), insert four leading bits from PC, and place the result in PC. This part is identical to the jump instruction for which the hardware already exists. For the first part, we insert two multiplexers at the write ports of the register file. The first multiplexer routes register address 31 into the write register address port. The second multiplexer routes the incremented value PC+4 into the write data port. Both multiplexers are controlled by the control logic, which also generates the RegWrite = 1 signal upon sensing the jal opcode. The following schematic is adopted from Lauren Goff. Problem 2: A single-cycle MIPS datapath contains memories, ALU and register file each requiring within 10ns to operate. The delay of other hardware is negligible. The processor is being designed for an instruction- specific (variable period) clocking using a fundamental external clock of period 10ns. Thus, the datapath clock period will be an instruction-specific multiple of 10ns. How many 10ns cycles should each type of instruction be given? Give the logic design for a clock generating circuit that will produce a clock signal for the program counter from the 10ns clock. Answer: The numbers of clock cycles for various types of instructions are: R-type 4 cycles lw 5 cycles sw 4 cycles branch 3 cycles jump 1 cycle