Computer Architecture and Design: Homework 6 Solutions for ELEC 5200-001/6200-001 - Prof. , Assignments of Computer Architecture and Organization

Download Computer Architecture and Design: Homework 6 Solutions for ELEC 5200-001/6200-001 - Prof. and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2007 Homework 6 Solution Assigned 3/23/07, due 4/4/07 Note: A useful, though not essential, reference is: B. Parhami, Computer Architecture from Microprocessors to Supercomputers, New York: Oxford, 2005. Problem 1: Write a MIPS instruction that reads from and writes to the same register. Sketch a schematic showing the execution of this instruction in a single- cycle MIPS datapath. In your schematic you may include only those units that participate in the execution of the instruction. If you are the designer how will you ensure that register read and write are done in the correct order? Answer: An instruction that reads and writes the same register: add rd, rs, rd # rd = rs + rd The following schematic shows a single-cycle datapath for this instruction. Notice that when new data is written in rd, its effect can circulate through the path shown in bold lines and change the content of rd repeatedly since the entire operation is done in the same clock cycle. This is a potential race condition. The execution cycle begins when the clock signal increments PC by +4 and activates fetching of the instruction from memory. Sensing the opcode, the control asserts Loop that can potentially corrupt the data written in the register file. RegWrite active add rd rt rs P C Instr. Memory Data Memory (not used) Select lower input Clock