Virtual Memory: Sharing Physical Memory among Processes, Study notes of School management&administration

Download Virtual Memory: Sharing Physical Memory among Processes and more Study notes School management&administration in PDF only on Docsity! 55:035 Computer Architecture and Organization Lecture 8 155:035 Computer Architecture and Organization Outline  Virtual Memory  Basics  Address Translation  Cache vs VM  Paging  Replacement  TLBs  Segmentation  Page Tables 255:035 Computer Architecture and Organization Virtual Memory  Virtual memory (VM) allows main memory (DRAM) to act like a cache for secondary storage (magnetic disk).  VM address translation a provides a mapping from the virtual address of the processor to the physical address in main memory or on disk. Compiler assigns data to a “virtual” address. VA translated to a real/physical somewhere in memory… (allows any program to run anywhere; where is determined by a particular machine, OS) 555:035 Computer Architecture and Organization VM Benefit  VM provides the following benefits  Allows multiple programs to share the same physical memory  Allows programmers to write code as though they have a very large amount of main memory  Automatically handles bringing in data from disk 655:035 Computer Architecture and Organization Virtual Memory Basics  Programs reference “virtual” addresses in a non-existent memory  These are then translated into real “physical” addresses  Virtual address space may be bigger than physical address space  Divide physical memory into blocks, called pages  Anywhere from 512 to 16MB (4k typical)  Virtual-to-physical translation by indexed table lookup  Add another cache for recent translations (the TLB)  Invisible to the programmer  Looks to your application like you have a lot of memory! 755:035 Computer Architecture and Organization Example of virtual memory  Relieves problem of making a program that was too large to fit in physical memory – well….fit!  Allows program to run in any location in physical memory  (called relocation)  Really useful as you might want to run same program on lots machines… 0 4 8 12 Virtual Address A B C D 0 4K 8K 12K Physical Address C A B D Disk 16K 20K 24K 28K Virtual Memory Physical Main Memory Logical program is in contiguous VA space; here, consists of 4 pages: A, B, C, D; The physical location of the 3 pages – 3 are in main memory and 1 is located on the disk 1055:035 Computer Architecture and Organization Cache terms vs. VM terms So, some definitions/“analogies”  A “page” or “segment” of memory is analogous to a “block” in a cache  A “page fault” or “address fault” is analogous to a cache miss “real”/physical memory so, if we go to main memory and our data isn’t there, we need to get it from disk… 1155:035 Computer Architecture and Organization More definitions and cache comparisons  These are more definitions than analogies…  With VM, CPU produces “virtual addresses” that are translated by a combination of HW/SW to “physical addresses”  The “physical addresses” access main memory  The process described above is called “memory mapping” or “address translation” 1255:035 Computer Architecture and Organization Virtual Memory Timing’s tough with virtual memory: AMAT = Tmem + (1-h) * Tdisk  = 100nS + (1-h) * 25,000,000nS h (hit rate) had to be incredibly (almost unattainably) close to perfect to work so: VM is a “cache” but an odd one. 1555:035 Computer Architecture and Organization Pages 55:035 Computer Architecture and Organization 16 Paging Hardware CPU page offset Physical Memory page table frame frame offset page 32 32 How big is a page? How big is the page table? 1755:035 Computer Architecture and Organization Test Yourself A processor asks for the contents of virtual memory address 0x10020. The paging scheme in use breaks this into a VPN of 0x10 and an offset of 0x020. PTR (a CPU register that holds the address of the page table) has a value of 0x100 indicating that this process’s page table starts at location 0x100. The machine uses word addressing and the page table entries are each one word long. PTR 0x100 Memory Reference VPN OFFSET 0x010 0x020 2055:035 Computer Architecture and Organization Test Yourself ADDR CONTENTS 0x00000 0x00000 0x00100 0x00010 0x00110 0x00022 0x00120 0x00045 0x00130 0x00078 0x00145 0x00010 0x10000 0x03333 0x10020 0x04444 0x22000 0x01111 0x22020 0x02222 0x45000 0x05555 0x45020 0x06666 • What is the physical address calculated? 1. 10020 2. 22020 3. 45000 4. 45020 5. none of the above PTR 0x100 Memory Reference VPN OFFSET 0x010 0x020 2155:035 Computer Architecture and Organization Test Yourself ADDR CONTENTS 0x00000 0x00000 0x00100 0x00010 0x00110 0x00022 0x00120 0x00045 0x00130 0x00078 0x00145 0x00010 0x10000 0x03333 0x10020 0x04444 0x22000 0x01111 0x22020 0x02222 0x45000 0x05555 0x45020 0x06666 • What is the physical address calculated? • What is the contents of this address returned to the processor? • How many memory accesses in total were required to obtain the contents of the desired address? PTR 0x100 Memory Reference VPN OFFSET 0x010 0x020 2255:035 Computer Architecture and Organization Block replacement  Which block should be replaced on a virtual memory miss?  Again, we’ll stick with the strategy that it’s a good thing to eliminate page faults  Therefore, we want to replace the LRU block  Many machines use a “use” or “reference” bit  Periodically reset  Gives the OS an estimation of which pages are referenced 2555:035 Computer Architecture and Organization Writing a block  What happens on a write?  We don’t even want to think about a write through policy!  Time with accesses, VM, hard disk, etc. is so great that this is not practical  Instead, a write back policy is used with a dirty bit to tell if a block has been written 2655:035 Computer Architecture and Organization Mechanism vs. Policy Mechanism:  paging hardware  trap on page fault Policy:  fetch policy: when should we bring in the pages of a process?  1. load all pages at the start of the process  2. load only on demand: “demand paging”  replacement policy: which page should we evict given a shortage of frames? 2755:035 Computer Architecture and Organization Page tables and lookups… 1. it’s slow! We’ve turned every access to memory into two accesses to memory  solution: add a specialized “cache” called a “translation lookaside buffer (TLB)” inside the processor 2. it’s still huge!  even worse: we’re ultimately going to have a page table for every process. Suppose 1024 processes, that’s 4GB of page tables! 3055:035 Computer Architecture and Organization Paging/VM (1/3) CPU 42 356 Physical Memory page table 356 i Operating System Disk 3155:035 Computer Architecture and Organization Paging/VM (2/3) CPU 42 356 Physical Memory 356 page table i Operating System Disk Place page table in physical memory However: this doubles the time per memory access!! 3255:035 Computer Architecture and Organization Translation Cache A way to speed up translation is to use a special cache of recently used page table entries -- this has many names, but the most frequently used is Translation Lookaside Buffer or TLB Virtual Page # Physical Frame # Dirty Ref Valid Access Really just a cache (a special-purpose cache) on the page table mappings TLB access time comparable to cache access time (much less than main memory access time) tag 3555:035 Computer Architecture and Organization An example of a TLB Page frame address Page Offset <30> <13> V <1> Tag <30> Phys. Addr. <21> ... … 1 2 32:1 Mux 3 4 R <2> W <2> … <21> <13> (Low-order 13 bits of addr.) (High-order 21 bits of addr.) 34-bit physical address Read/write policies and permissions… 3655:035 Computer Architecture and Organization The “big picture” and TLBs  Address translation is usually on the critical path…  …which determines the clock cycle time of the mP  Even in the simplest cache, TLB values must be read and compared  TLB is usually smaller and faster than the cache- address-tag memory  This way multiple TLB reads don’t increase the cache hit time  TLB accesses are usually pipelined b/c its so important! 3755:035 Computer Architecture and Organization Normal Page Tables  Size is number of virtual pages  Purpose is to hold the translation of VPN to PPN  Permits ease of page relocation  Make sure to keep tags to indicate page is mapped  Potential problem:  Consider 32bit virtual address and 4k pages  4GB/4KB = 1MW required just for the page table!  Might have to page in the page table…  Consider how the problem gets worse on 64bit machines with even larger virtual address spaces!  Might have multi-level page tables 4055:035 Computer Architecture and Organization Inverted Page Tables  Similar to a set-associative mechanism  Make the page table reflect the # of physical pages (not virtual)  Use a hash mechanism  virtual page number ==> HPN index into inverted page table  Compare virtual page number with the tag to make sure it is the one you want  if yes  check to see that it is in memory - OK if yes - if not page fault  If not - miss  go to full page table on disk to get new entry  implies 2 disk accesses in the worst case  trades increased worst case penalty for decrease in capacity induced miss rate since there is now more room for real pages with smaller page table 4155:035 Computer Architecture and Organization Inverted Page Table Page V Page Offset Frame Offset FrameHash = OK •Only store entries for pages in physical memory 4255:035 Computer Architecture and Organization Last Question  Q4: Write Policy  Always write-back  Due to the access time of the disk  So, you need to keep tags to show when pages are dirty and need to be written back to disk when they’re swapped out.  Anything else is pretty silly  Remember – the disk is SLOW! 4555:035 Computer Architecture and Organization Page Sizes  An architectural choice  Large pages are good:  reduces page table size  amortizes the long disk access  if spatial locality is good then hit rate will improve  Large pages are bad:  more internal fragmentation  if everything is random each structure’s last page is only half full  Half of bigger is still bigger  if there are 3 structures per process: text, heap, and control stack  then 1.5 pages are wasted for each process  process start up time takes longer  since at least 1 page of each type is required to prior to start  transfer time penalty aspect is higher 4655:035 Computer Architecture and Organization More on TLBs  The TLB must be on chip  otherwise it is worthless  small TLB’s are worthless anyway  large TLB’s are expensive  high associativity is likely  ==> Price of CPU’s is going up!  OK as long as performance goes up faster 4755:035 Computer Architecture and Organization Pitfall: Address space to small  One of the biggest mistakes than can be made when designing an architecture is to devote to few bits to the address  address size limits the size of virtual memory  difficult to change since many components depend on it (e.g., PC, registers, effective-address calculations)  As program size increases, larger and larger address sizes are needed  8 bit: Intel 8080 (1975)  16 bit: Intel 8086 (1978)  24 bit: Intel 80286 (1982)  32 bit: Intel 80386 (1985)  64 bit: Intel Merced (1998) 5055:035 Computer Architecture and Organization Virtual Memory Summary  Virtual memory (VM) allows main memory (DRAM) to act like a cache for secondary storage (magnetic disk).  The large miss penalty of virtual memory leads to different stategies from cache  Fully associative, TB + PT, LRU, Write-back  Designed as  paged: fixed size blocks  segmented: variable size blocks  hybrid: segmented paging or multiple page sizes  Avoid small address size 5155:035 Computer Architecture and Organization Summary 2: Typical Choices Option TLB L1 Cache L2 Cache VM (page) Block Size 4-8 bytes (1 PTE) 4-32 bytes 32-256 bytes 4k-16k bytes Hit Time 1 cycle 1-2 cycles 6-15 cycles 10-100 cycles Miss Penalty 10-30 cycles 8-66 cycles 30-200 cycles 700k-6M cycles Local Miss Rate .1 - 2% .5 – 20% 13 - 15% .00001 - 001% Size 32B – 8KB 1 – 128 KB 256KB - 16MB Backing Store L1 Cache L2 Cache DRAM Disks Q1: Block Placement Fully or set associative DM DM or SA Fully associative Q2: Block ID Tag/block Tag/block Tag/block Table Q3: Block Replacement Random (not last) N.A. For DM Random (if SA) LRU/LFU Q4: Writes Flush on PTE write Through or back Write-back Write-back 5255:035 Computer Architecture and Organization