Computer Architecture Comprehensive Exam, Exams of Computer Architecture and Organization

Download Computer Architecture Comprehensive Exam and more Exams Computer Architecture and Organization in PDF only on Docsity! - 1 of 10 - Stanford University 10 November 2005 Computer Architecture Comprehensive Exam Exam Instructions Answer each of the questions included in the exam. Write all of your answers directly on the examination paper, including any work that you wish to be considered for partial credit. The examination is open-book, and you may make use of the text, handouts, your own course notes, and a calculator. You may use a computer of any kind but no network. On equations: Wherever possible, make sure to include the equation, the equation rewritten with the numerical values, and the final solution. Partial credit will be weighted appropriately for each component of the problem, and providing more information improves the likelihood that partial credit can be awarded. On writing code: Unless otherwise stated, you are free to use any of the assembly instructions listed in the Appendix at the back of the book, including pseudoinstructions. You do not need to optimize your MIPS code unless specifically instructed to do so. On time: You will have one hour to complete this exam. Budget your time and try to leave some time at the end to go over your work. The point weightings correspond roughly to the time each problem is expected to take. THE STANFORD UNIVERSITY HONOR CODE The Honor Code is an undertaking of the students, individually and collectively: (1) that they will not give or receive aid in examinations; that they will not give or receive unpermitted aid in class work, in the preparation of reports, or in any other work that is to be used by the instructor as the basis of grading; (2) that they will do their share and take an active part in seeing to it that others as well as themselves uphold the spirit and letter of the Honor Code. I acknowledge and accept the Honor Code. Magic Number __________________________________________________________ Score Grader 1. Short Answer (15) ______ ______ 2. ISA (15) ______ ______ 3. Pipelining (15) ______ ______ 4. Cache (15) ______ ______ Total (60) ______ - 2 of 10 - Problem 1: Short Answer (15 points) Please provide short, concise answers. (a) [3 points] Can a direct mapped cache sometimes have a higher hit rate than a fully associative cache with an LRU replacement policy (on the same reference pattern and with the same cache size)? If so, give an example. If not, explain why not? (b) [3 points] Give two ways virtual memory address translation is useful even if the total size of virtual memory (summed over all programs) is guaranteed to be smaller than physical memory. - 5 of 10 - (b) [4 points] Give an example of a code sequence where the compiler could not perform this replacement even though it matches the general pattern? (c) [3 points] Considering the usual 5 stage MIPS pipeline, why might this new instruction be problematic to implement with no change in CPI? - 6 of 10 - Problem 3: Pipelining (15 points) Consider the following code: Loop:lw $1, 0($2) addi $1, $1, 1 sw $1, 0($2) addi $2, $2, 4 sub $4, $3, $2 bne $4, $0, Loop Assume that the initial value or R3 is R2 + 396 This code snippet will be executed on a MIPS pipelined processor with a 5-stage pipeline. Branches are resolved in the decode stage and do not have delay slots. All memory accesses take 1 clock cycle. In the following three parts, you will be filling out pipeline diagrams for the above code sequence. Please use acronyms F, D, X, M and W for the 5 pipeline stages. For all cases of forwarding, use arrows to connect the source and destination stages. Simulate at most 7 instructions, making one pass through the loop and performing the first instruction a second time. (a) [5 points] Fill in the pipeline diagram below for the execution of the above code sequence without any forwarding or bypassing hardware but assuming a register read and a write in the same clock cycle “forwards” through the register file. Cycle Instruction 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 7 of 10 - (b) [5 points] Fill in the pipeline diagram below for the execution of the above code sequence with traditional pipeline forwarding: Cycle Instruction 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (c) [5 points] Aggressively rearrange the order of the instructions (data dependencies have to be preserved) so that the number of instructions/cycles needed to execute the code snippet is minimized. Fill in the following table with the rearranged instruction sequence assuming traditional pipeline forwarding like part (b): Cycle Instruction 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16